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authorJames Yang <James.Yang@freescale.com>2010-01-12 15:50:18 -0600
committerKumar Gala <galak@kernel.crashing.org>2010-01-25 22:13:25 -0600
commit93cedc71647b4b72ac9b48e11997eb2f91645001 (patch)
treef2a40f94836d6c79f26d7d4dea94aa323ae477bd /cpu/mpc85xx/speed.c
parent2903ad33a71251a3a87485b5b185852c8998f209 (diff)
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ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT
The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/speed.c')
-rw-r--r--cpu/mpc85xx/speed.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 2103e2e..8dab8d1 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo)
freqCC_PLL[2] = sysclk;
freqCC_PLL[3] = sysclk;
- sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
- sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
+ sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;