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authorWolfgang Grandegger <wg@grandegger.com>2008-09-30 10:55:57 +0200
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-10-08 14:20:27 -0500
commitdffd2446fb041f38ef034b0fcf41e51e5e489159 (patch)
tree0a5da83e67172e86ef0277c88ef943225744c048 /cpu/mpc85xx/speed.c
parente46c7bfb8bc3c304cedd20f7a365d6e78d7eaf17 (diff)
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85xx: Using proper I2C source clock divider for MPC8544
Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Diffstat (limited to 'cpu/mpc85xx/speed.c')
-rw-r--r--cpu/mpc85xx/speed.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 485ba20..70dfad0 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -102,9 +102,9 @@ int get_clocks (void)
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->i2c1_clk = sys_info.freqSystemBus / 3;
- else
gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ else
+ gd->i2c1_clk = sys_info.freqSystemBus / 3;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
gd->i2c1_clk = sys_info.freqSystemBus / 2;