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| author | Wolfgang Denk <wd@denx.de> | 2008-01-23 13:56:55 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-01-23 13:56:55 +0100 |
| commit | 39166b5c9e7160761419f816f995b1d8029aa4a7 (patch) | |
| tree | 45ec07fd02acb2338351b978194732af56c480a7 /cpu/mpc85xx/spd_sdram.c | |
| parent | cfe5ca77976afdbe7ecb86e39fd7505bde636ace (diff) | |
| parent | 6ea66a818de376ff599c40bdd6c361cfcba2fb6f (diff) | |
| download | u-boot-imx-39166b5c9e7160761419f816f995b1d8029aa4a7.zip u-boot-imx-39166b5c9e7160761419f816f995b1d8029aa4a7.tar.gz u-boot-imx-39166b5c9e7160761419f816f995b1d8029aa4a7.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'cpu/mpc85xx/spd_sdram.c')
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 28 |
1 files changed, 8 insertions, 20 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index adc9c4d..abc63c4 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -27,6 +27,7 @@ #include <i2c.h> #include <spd.h> #include <asm/mmu.h> +#include <asm/fsl_law.h> #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) @@ -1022,7 +1023,6 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0)); - mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))); - asm volatile("isync;msync;tlbwe;isync"); - - debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0)); - debug("DDR: MAS3=0x%08x\n", - FSL_BOOKE_MAS3(ram_tlb_address, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))); + set_tlb(1, ram_tlb_address, ram_tlb_address, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, ram_tlb_index, tlb_size, 1); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; @@ -1098,12 +1088,10 @@ setup_laws_and_tlbs(unsigned int memsize) /* * Set up LAWBAR for all of DDR. */ - ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - ecm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR - | (LAWAR_SIZE & law_size)); - debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1); - debug("DDR: LARAR1=0x%08x\n", ecm->lawar1); + +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); +#endif /* * Confirm that the requested amount of memory was mapped. |