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| author | Jon Loeliger <jdl@freescale.com> | 2008-01-10 14:28:18 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-01-10 14:28:18 -0600 |
| commit | bb66f5613672fc80a6b38a0e1651d893bbe590a5 (patch) | |
| tree | 9a8af7224b4dc2162a5cec00cf44d5afae43622f /cpu/mpc85xx/spd_sdram.c | |
| parent | b830b7f1635984ba607219fcbd78597c28eeb529 (diff) | |
| parent | 422b1a01602b6e2fbf8444a1192c7ba31461fd4c (diff) | |
| download | u-boot-imx-bb66f5613672fc80a6b38a0e1651d893bbe590a5.zip u-boot-imx-bb66f5613672fc80a6b38a0e1651d893bbe590a5.tar.gz u-boot-imx-bb66f5613672fc80a6b38a0e1651d893bbe590a5.tar.bz2 | |
Merge commit 'wd/master'
Diffstat (limited to 'cpu/mpc85xx/spd_sdram.c')
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 553f736..adc9c4d 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); - mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0)); + mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); asm volatile("isync;msync;tlbwe;isync"); - debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", - TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0)); debug("DDR: MAS3=0x%08x\n", - TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; |