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authorKumar Gala <galak@kernel.crashing.org>2008-01-16 22:33:22 -0600
committerKumar Gala <galak@kernel.crashing.org>2008-01-17 02:04:07 -0600
commit44a23cfd6360a68eaa41f945190618a55519eac3 (patch)
treede0fba321ba3ebe9bba235490fd94e82a2576c82 /cpu/mpc85xx/spd_sdram.c
parentc8c41d4a80b1a8ad5984a287d81ea780496259f8 (diff)
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85xx: Introduce new tlb API
Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/spd_sdram.c')
-rw-r--r--cpu/mpc85xx/spd_sdram.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 90c3d44..abc63c4 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize)
ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize * 1024 * 1024)
&& ram_tlb_index < 16) {
- mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
- mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
- mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
- mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR)));
- asm volatile("isync;msync;tlbwe;isync");
-
- debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
- debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
- debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
- debug("DDR: MAS3=0x%08x\n",
- FSL_BOOKE_MAS3(ram_tlb_address, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR)));
+ set_tlb(1, ram_tlb_address, ram_tlb_address,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, ram_tlb_index, tlb_size, 1);
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
ram_tlb_index++;