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| author | Andy Fleming <afleming@freescale.com> | 2007-08-13 14:49:59 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-08-14 01:44:55 -0500 |
| commit | 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a (patch) | |
| tree | 2cbe4098e743b3e178ddb3bc97ca8ef9ec7107cd /cpu/mpc85xx/spd_sdram.c | |
| parent | 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 (diff) | |
| download | u-boot-imx-39980c610c9a4c381907c9e1d1b9c0e1c0dca57a.zip u-boot-imx-39980c610c9a4c381907c9e1d1b9c0e1c0dca57a.tar.gz u-boot-imx-39980c610c9a4c381907c9e1d1b9c0e1c0dca57a.tar.bz2 | |
MPC85xx BA bits not set for 3-bit bank address DIMM
The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).
Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
Diffstat (limited to 'cpu/mpc85xx/spd_sdram.c')
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index d984554..679f360 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -176,7 +176,7 @@ spd_sdram(void) spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; unsigned int odt_cfg, mode_odt_enable; unsigned int refresh_clk; #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL @@ -341,9 +341,14 @@ spd_sdram(void) #endif } + ba_bits = 0; + if (spd.nbanks == 0x8) + ba_bits = 1; + ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); |