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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-19 02:53:01 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:02 -0600 |
| commit | 82fd1f8da9add2d74532cf78d224485f0042d00d (patch) | |
| tree | 40c31ab6b1538c54882294ad7f2752ca60097910 /cpu/mpc85xx/release.S | |
| parent | 6ca9da4d42aeb43df5ef29f7d0518009df583b2f (diff) | |
| download | u-boot-imx-82fd1f8da9add2d74532cf78d224485f0042d00d.zip u-boot-imx-82fd1f8da9add2d74532cf78d224485f0042d00d.tar.gz u-boot-imx-82fd1f8da9add2d74532cf78d224485f0042d00d.tar.bz2 | |
85xx: Add support for e500mc cache stashing
The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.
We use the following equation to set the various stash-ids:
32 + coreID*2 + 0(L1) or 1(L2)
The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/release.S')
| -rw-r--r-- | cpu/mpc85xx/release.S | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 433ff02..55eca72 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -99,6 +99,13 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync @@ -110,6 +117,12 @@ __secondary_start_page: and. r1,r3,r2 bne 1b +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + addi r3,r8,1 + mtspr SPRN_L2CSR1,r3 +#endif + lis r3,CONFIG_SYS_INIT_L2CSR0@h ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 |