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authorKumar Gala <galak@kernel.crashing.org>2008-10-23 01:47:38 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-10-24 15:10:47 -0500
commit0f060c3bf82832331a509f2e5d2442539e7aad09 (patch)
tree08d890ed38595a17dc4b126847a7dce31c69cd5d /cpu/mpc85xx/release.S
parenta38a5b6edd30f29fd5fdb1d7f674521906c0e677 (diff)
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85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/release.S')
-rw-r--r--cpu/mpc85xx/release.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index ec5e4da..7c3e8a1 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -24,14 +24,18 @@
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
+#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
+#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
+#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
+#endif
/* Enable branch prediction */
li r3,0x201
@@ -64,7 +68,11 @@ __secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+ rlwinm r4,r0,27,27,31
+#else
mr r4,r0
+#endif
slwi r8,r4,5
add r10,r3,r8