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| author | Andy Fleming <afleming@freescale.com> | 2007-08-14 01:34:21 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-08-14 01:34:21 -0500 |
| commit | 61a21e980a7b9188424d04f1c265fdc5c21c7e85 (patch) | |
| tree | 9037e89c6f5ccb72b5e8b1dc150c6b0afd569531 /cpu/mpc85xx/interrupts.c | |
| parent | 7bd30fc4a6475b41d6679ae3aafc9fa505260c47 (diff) | |
| download | u-boot-imx-61a21e980a7b9188424d04f1c265fdc5c21c7e85.zip u-boot-imx-61a21e980a7b9188424d04f1c265fdc5c21c7e85.tar.gz u-boot-imx-61a21e980a7b9188424d04f1c265fdc5c21c7e85.tar.bz2 | |
85xx start.S cleanup and exception support
From: Ed Swarthout <Ed.Swarthout@freescale.com>
Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.
Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.
Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl
Move additional code from .text to boot page to make room for
exception vectors at start of image.
Handle Machine Check, External and Critical exceptions.
Fix e500 machine check error determination in traps.c
TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/mpc85xx/interrupts.c')
| -rw-r--r-- | cpu/mpc85xx/interrupts.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index dc246dc..bf737d6 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -89,6 +89,39 @@ int interrupt_init (void) mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); + +#ifdef CONFIG_INTERRUPTS + volatile ccsr_pic_t *pic = &immr->im_pic; + + pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3); + +#ifdef CONFIG_PCI1 + pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ + debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ + debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9); +#endif +#ifdef CONFIG_PCIE1 + pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ + debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10); +#endif +#ifdef CONFIG_PCIE3 + pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ + debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11); +#endif + + pic->ctpr=0; /* 40080 clear current task priority register */ +#endif + return (0); } |