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| author | Wolfgang Denk <wd@denx.de> | 2008-10-27 22:31:32 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-27 22:31:32 +0100 |
| commit | f8030519bbe20b836f3939742b959cbadfaad51b (patch) | |
| tree | ae23fde6c7c196fca5fb62d6e30103974179d961 /cpu/mpc85xx/ddr-gen3.c | |
| parent | 5deb8022c3749faac30e9ad9694691e2442b5c93 (diff) | |
| parent | c2083e0e11a03ef8be2e9f0ed8720fdc20832f3e (diff) | |
| download | u-boot-imx-f8030519bbe20b836f3939742b959cbadfaad51b.zip u-boot-imx-f8030519bbe20b836f3939742b959cbadfaad51b.tar.gz u-boot-imx-f8030519bbe20b836f3939742b959cbadfaad51b.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'cpu/mpc85xx/ddr-gen3.c')
| -rw-r--r-- | cpu/mpc85xx/ddr-gen3.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index e0654bb..a2b45c5 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -79,15 +79,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); /* - * 32-bit workaround for DDR2 - * 32_BE + * For 8572 DDR1 erratum - DDR controller may enter illegal state + * when operatiing in 32-bit bus mode with 4-beat bursts, + * This erratum does not affect DDR3 mode, only for DDR2 mode. */ +#ifdef CONFIG_MPC8572 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) - && in_be32(&ddr->sdram_cfg_2) & 0x80000) { + && in_be32(&ddr->sdram_cfg) & 0x80000) { /* set DEBUG_1[31] */ u32 temp = in_be32(&ddr->debug_1); out_be32(&ddr->debug_1, temp | 1); } +#endif /* * 200 painful micro-seconds must elapse between |