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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-11-13 09:04:19 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:08 -0600 |
| commit | 355f4f85e90ce2e6d91883012c2993be7970c8b1 (patch) | |
| tree | 7380c8c9cd3d6464f0da09767b7fcd3ccf41c06a /cpu/mpc85xx/ddr-gen1.c | |
| parent | 94e9411b9dda182dd63d53ba6ea640c98b35db5f (diff) | |
| download | u-boot-imx-355f4f85e90ce2e6d91883012c2993be7970c8b1.zip u-boot-imx-355f4f85e90ce2e6d91883012c2993be7970c8b1.tar.gz u-boot-imx-355f4f85e90ce2e6d91883012c2993be7970c8b1.tar.bz2 | |
ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
Now that we track which TLB CAM entries are used we can allocate
entries on the fly. Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/ddr-gen1.c')
0 files changed, 0 insertions, 0 deletions