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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-11 13:52:45 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-15 21:30:09 -0500 |
| commit | 9f00409a9d04cf533305531da32437130802f3a3 (patch) | |
| tree | 0f1d7791cc318282fcf78e46b637ea9aeadedb3d /cpu/mpc85xx/cpu_init.c | |
| parent | 0456dbf3475d0aec42873a967ac97ed81f376119 (diff) | |
| download | u-boot-imx-9f00409a9d04cf533305531da32437130802f3a3.zip u-boot-imx-9f00409a9d04cf533305531da32437130802f3a3.tar.gz u-boot-imx-9f00409a9d04cf533305531da32437130802f3a3.tar.bz2 | |
ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL
By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 07856c2..48a82ed 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -129,57 +129,6 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif -/* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) -{ - u32 mas0, mas1, mas2, mas3, mas7; - int i; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* - * Clear initial global data - * we don't use memset so we can share this code with NAND_SPL - */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - /* set up CCSR if we want it moved */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - { - u32 temp; - volatile u32 *ccsr_virt = - (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, - MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); - } -#endif - - init_laws(); - invalidate_tlb(0); - init_tlbs(); -} - /* * Breathe some life into the CPU... * |