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| author | Kumar Gala <galak@kernel.crashing.org> | 2007-11-29 02:10:09 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-12-11 22:34:20 -0600 |
| commit | 04db400892da37b76a585e332a0c137954ad2015 (patch) | |
| tree | 201c757a3032f786588d94c0fde8469a865b40b5 /cpu/mpc85xx/cpu_init.c | |
| parent | 2714223f8e04ab3e4133ff65872eef366d90bfea (diff) | |
| download | u-boot-imx-04db400892da37b76a585e332a0c137954ad2015.zip u-boot-imx-04db400892da37b76a585e332a0c137954ad2015.tar.gz u-boot-imx-04db400892da37b76a585e332a0c137954ad2015.tar.bz2 | |
Stop using immap_t on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5af69ce..fdb9ecb 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -131,8 +131,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) void cpu_init_f (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); /* Pointer is writable since we allocated a register for it */ @@ -222,18 +221,15 @@ void cpu_init_f (void) int cpu_init_r(void) { -#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#endif #ifdef CONFIG_CLEAR_LAW0 - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; uint l2srbar; |