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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-17 01:52:37 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-24 12:05:29 -0500 |
| commit | 3c2a67eec8a0facc865b400caca52e7f6b7adf01 (patch) | |
| tree | 131a11003534635f5ae7a948ee4202e1e2d1c711 /cpu/mpc85xx/cpu.c | |
| parent | 7e4259bba4c56536760e42d32dacfb3233f216fd (diff) | |
| download | u-boot-imx-3c2a67eec8a0facc865b400caca52e7f6b7adf01.zip u-boot-imx-3c2a67eec8a0facc865b400caca52e7f6b7adf01.tar.gz u-boot-imx-3c2a67eec8a0facc865b400caca52e7f6b7adf01.tar.bz2 | |
ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/cpu.c')
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4..25c0416 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif } |