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authorJason Jin <Jason.jin@freescale.com>2008-09-27 14:40:57 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-10-07 15:37:08 -0500
commitc0391111c33c22fabeddf8f4ca801ec7645b4f5c (patch)
tree38f34ae2b3cdb04300ee0c5afb08e9317c2e5d05 /cpu/mpc85xx/cpu.c
parentbac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4 (diff)
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Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Diffstat (limited to 'cpu/mpc85xx/cpu.c')
-rw-r--r--cpu/mpc85xx/cpu.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 67e81c0..f15b0a8 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -85,7 +85,8 @@ int checkcpu (void)
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif