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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-03-27 17:02:44 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-03-30 13:33:51 -0500 |
| commit | 22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4 (patch) | |
| tree | 611cd5baec5cb44cb29fc46a2d2d8f7fb8ba23e6 /cpu/mpc85xx/Makefile | |
| parent | 2d4de6ae5be54b367a72a7ef4e0cf36a9cd4881f (diff) | |
| download | u-boot-imx-22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4.zip u-boot-imx-22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4.tar.gz u-boot-imx-22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4.tar.bz2 | |
MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/Makefile')
| -rw-r--r-- | cpu/mpc85xx/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 99d88a8..8809302 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_MPC8569) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ |