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author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 01:05:35 -0500 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:53 -0500 |
commit | 457caecdbca3df21a93abff19eab12dbc61b7897 (patch) | |
tree | dd6cdf741c7757425d33567b01cb7907dec0096e /cpu/mpc85xx/Makefile | |
parent | 0e7927db138976469e7257e29c1338050a50fcd9 (diff) | |
download | u-boot-imx-457caecdbca3df21a93abff19eab12dbc61b7897.zip u-boot-imx-457caecdbca3df21a93abff19eab12dbc61b7897.tar.gz u-boot-imx-457caecdbca3df21a93abff19eab12dbc61b7897.tar.bz2 |
FSL DDR: Remove old SPD support from cpu/mpc85xx
All 85xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/Makefile')
-rw-r--r-- | cpu/mpc85xx/Makefile | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 3a3c6a7..80b80ff 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -35,15 +35,12 @@ COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o # supports ddr1 -ifeq ($(CONFIG_FSL_DDR1),y) COBJS-$(CONFIG_MPC8540) += ddr-gen1.o COBJS-$(CONFIG_MPC8560) += ddr-gen1.o COBJS-$(CONFIG_MPC8541) += ddr-gen1.o COBJS-$(CONFIG_MPC8555) += ddr-gen1.o -endif # supports ddr1/2 -ifeq ($(CONFIG_FSL_DDR2),y) COBJS-$(CONFIG_MPC8548) += ddr-gen2.o COBJS-$(CONFIG_MPC8568) += ddr-gen2.o COBJS-$(CONFIG_MPC8544) += ddr-gen2.o @@ -51,15 +48,6 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o -endif - -ifneq ($(CONFIG_FSL_DDR3),y) -ifneq ($(CONFIG_FSL_DDR2),y) -ifneq ($(CONFIG_FSL_DDR1),y) -COBJS-y += spd_sdram.o -endif -endif -endif COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \ |