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authorXie Xiaobo <r63061@freescale.com>2007-03-09 19:08:25 +0800
committerKim Phillips <kim.phillips@freescale.com>2007-04-12 17:39:03 -0500
commit6fbf261f8df294e589cfadebebe5468e3c0f29e9 (patch)
tree592fb707b77e2a37a5259119149566192a7d7e49 /cpu/mpc83xx
parentaea17f99278818caa327ad0e511b48d1761fb10c (diff)
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Fix two bugs for MPC83xx DDR2 controller SPD Init
There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
Diffstat (limited to 'cpu/mpc83xx')
-rw-r--r--cpu/mpc83xx/spd_sdram.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753..41a1f1f 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
int clks;
ddr_bus_clk = gd->ddr_clk >> 1;
- clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
- if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+ clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+ if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
clks++;
return clks;
@@ -624,7 +624,7 @@ long int spd_sdram()
| (1 << (16 + 10)) /* DQS Differential disable */
| (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
| (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
- | ((twr_clk >> 1) << 9) /* Write Recovery Autopre */
+ | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
| (caslat << 4) /* caslat */
| (burstlen << 0) /* Burst length */
);