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authorNick Spence <nick.spence@freescale.com>2008-08-22 23:52:50 -0700
committerKim Phillips <kim.phillips@freescale.com>2008-09-03 16:06:46 -0500
commitd9fe88173cb4f7d293796ffe10c7a0d3d426d8f9 (patch)
tree1e41ed69bee55104040500de9cbfd8f86bc896c6 /cpu/mpc83xx
parent628ffd73bcff0c9f3bc5a8eeb2c7455fe9d28a51 (diff)
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MPC83XX: Fix GPIO configuration - set gpio level before direction
Set DAT value before DIR values to avoid creating glitches on the GPIO signals. Set gpio level register before direction register to inhibit glitches on high level output pins. Dir and data gets cleared at powerup, so high level output lines see a short low pulse between setting the direction and level registers. Issue was seen on a new board with the nReset line of the NOR flash connected to a GPIO. Setting the direction register puts the NOR flash in reset so the next instruction to set the level cannot get executed. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'cpu/mpc83xx')
-rw-r--r--cpu/mpc83xx/cpu_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 67c9e57..4514dbb 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -283,12 +283,12 @@ void cpu_init_f (volatile immap_t * im)
im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
#endif
#ifdef CFG_GPIO1_PRELIM
- im->gpio[0].dir = CFG_GPIO1_DIR;
im->gpio[0].dat = CFG_GPIO1_DAT;
+ im->gpio[0].dir = CFG_GPIO1_DIR;
#endif
#ifdef CFG_GPIO2_PRELIM
- im->gpio[1].dir = CFG_GPIO2_DIR;
im->gpio[1].dat = CFG_GPIO2_DAT;
+ im->gpio[1].dir = CFG_GPIO2_DIR;
#endif
}