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authorAnton Vorontsov <avorontsov@ru.mvista.com>2008-10-02 18:31:56 +0400
committerKim Phillips <kim.phillips@freescale.com>2008-10-21 18:34:01 -0500
commit6f9cc6608b4e1cefde56c0fb99ae1c95c42575ff (patch)
treeaf7d9a23b6f49f81ae1e67510607f1244fc2c94f /cpu/mpc83xx
parent55c531984dcf933e4cd13a187a7e08e873b7ced1 (diff)
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mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'cpu/mpc83xx')
-rw-r--r--cpu/mpc83xx/serdes.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
index 630b111..3936796 100644
--- a/cpu/mpc83xx/serdes.c
+++ b/cpu/mpc83xx/serdes.c
@@ -42,7 +42,7 @@
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
-void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd)
+void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
{
void *regs = (void *)CONFIG_SYS_IMMR + offset;
u32 tmp;