Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx

Conflicts:

	lib_ppc/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

4 files changed, 70 insertions, 144 deletions

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index bff3cef..36de78d 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -42,6 +42,30 @@ int checkcpu(void)
 	u32 pvr = get_pvr();
 	u32 spridr;
 	char buf[32];
+	int i;
+
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+	const struct cpu_type {
+		char name[15];
+		u32 partid;
+	} cpu_type_list [] = {
+		CPU_TYPE_ENTRY(8311),
+		CPU_TYPE_ENTRY(8313),
+		CPU_TYPE_ENTRY(8314),
+		CPU_TYPE_ENTRY(8315),
+		CPU_TYPE_ENTRY(8321),
+		CPU_TYPE_ENTRY(8323),
+		CPU_TYPE_ENTRY(8343),
+		CPU_TYPE_ENTRY(8347_TBGA_),
+		CPU_TYPE_ENTRY(8347_PBGA_),
+		CPU_TYPE_ENTRY(8349),
+		CPU_TYPE_ENTRY(8358_TBGA_),
+		CPU_TYPE_ENTRY(8358_PBGA_),
+		CPU_TYPE_ENTRY(8360),
+		CPU_TYPE_ENTRY(8377),
+		CPU_TYPE_ENTRY(8378),
+		CPU_TYPE_ENTRY(8379),
+	};
 
 	immr = (immap_t *)CFG_IMMR;
 
@@ -69,130 +93,26 @@ int checkcpu(void)
 	}
 
 	spridr = immr->sysconf.spridr;
-	switch(spridr) {
-	case SPR_8349E_REV10:
-	case SPR_8349E_REV11:
-	case SPR_8349E_REV31:
-		puts("MPC8349E, ");
-		break;
-	case SPR_8349_REV10:
-	case SPR_8349_REV11:
-	case SPR_8349_REV31:
-		puts("MPC8349, ");
-		break;
-	case SPR_8347E_REV10_TBGA:
-	case SPR_8347E_REV11_TBGA:
-	case SPR_8347E_REV31_TBGA:
-	case SPR_8347E_REV10_PBGA:
-	case SPR_8347E_REV11_PBGA:
-	case SPR_8347E_REV31_PBGA:
-		puts("MPC8347E, ");
-		break;
-	case SPR_8347_REV10_TBGA:
-	case SPR_8347_REV11_TBGA:
-	case SPR_8347_REV31_TBGA:
-	case SPR_8347_REV10_PBGA:
-	case SPR_8347_REV11_PBGA:
-	case SPR_8347_REV31_PBGA:
-		puts("MPC8347, ");
-		break;
-	case SPR_8343E_REV10:
-	case SPR_8343E_REV11:
-	case SPR_8343E_REV31:
-		puts("MPC8343E, ");
-		break;
-	case SPR_8343_REV10:
-	case SPR_8343_REV11:
-	case SPR_8343_REV31:
-		puts("MPC8343, ");
-		break;
-	case SPR_8360E_REV10:
-	case SPR_8360E_REV11:
-	case SPR_8360E_REV12:
-	case SPR_8360E_REV20:
-	case SPR_8360E_REV21:
-		puts("MPC8360E, ");
-		break;
-	case SPR_8360_REV10:
-	case SPR_8360_REV11:
-	case SPR_8360_REV12:
-	case SPR_8360_REV20:
-	case SPR_8360_REV21:
-		puts("MPC8360, ");
-		break;
-	case SPR_8323E_REV10:
-	case SPR_8323E_REV11:
-		puts("MPC8323E, ");
-		break;
-	case SPR_8323_REV10:
-	case SPR_8323_REV11:
-		puts("MPC8323, ");
-		break;
-	case SPR_8321E_REV10:
-	case SPR_8321E_REV11:
-		puts("MPC8321E, ");
-		break;
-	case SPR_8321_REV10:
-	case SPR_8321_REV11:
-		puts("MPC8321, ");
-		break;
-	case SPR_8311_REV10:
-		puts("MPC8311, ");
-		break;
-	case SPR_8311E_REV10:
-		puts("MPC8311E, ");
-		break;
-	case SPR_8313_REV10:
-		puts("MPC8313, ");
-		break;
-	case SPR_8313E_REV10:
-		puts("MPC8313E, ");
-		break;
-	case SPR_8315E_REV10:
-		puts("MPC8315E, ");
-		break;
-	case SPR_8315_REV10:
-		puts("MPC8315, ");
-		break;
-	case SPR_8314E_REV10:
-		puts("MPC8314E, ");
-		break;
-	case SPR_8314_REV10:
-		puts("MPC8314, ");
-		break;
-	case SPR_8379E_REV10:
-		puts("MPC8379E, ");
-		break;
-	case SPR_8379_REV10:
-		puts("MPC8379, ");
-		break;
-	case SPR_8378E_REV10:
-		puts("MPC8378E, ");
-		break;
-	case SPR_8378_REV10:
-		puts("MPC8378, ");
-		break;
-	case SPR_8377E_REV10:
-		puts("MPC8377E, ");
-		break;
-	case SPR_8377_REV10:
-		puts("MPC8377, ");
-		break;
-	default:
-		printf("Rev: Unknown revision number:%08x\n"
-			"Warning: Unsupported cpu revision!\n",spridr);
-		return 0;
-	}
 
-#if defined(CONFIG_MPC834X)
-	/* Multiple revisons of 834x processors may have the same SPRIDR value.
-	 * So use PVR to identify the revision number.
-	 */
-	printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
-#else
-	printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
-#endif
-	printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
+	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+		if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
+			puts("MPC");
+			puts(cpu_type_list[i].name);
+			if (IS_E_PROCESSOR(spridr))
+				puts("E");
+			if (REVID_MAJOR(spridr) >= 2)
+				puts("A");
+			printf(", Rev: %d.%d", REVID_MAJOR(spridr),
+			       REVID_MINOR(spridr));
+			break;
+		}
+
+	if (i == ARRAY_SIZE(cpu_type_list))
+		printf("(SPRIDR %08x unknown), ", spridr);
+
+	printf(" at %s MHz, ", strmhz(buf, clock));
+
+	printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
 
 	return 0;
 }
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 0acca47..97ac7bb 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -34,10 +34,13 @@
 #include <asm/mmu.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void board_add_ram_info(int use_default)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile ddr83xx_t *ddr = &immap->ddr;
+	char buf[32];
 
 	printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
 			   >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
@@ -48,9 +51,11 @@ void board_add_ram_info(int use_default)
 		puts(", 64-bit");
 
 	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
-		puts(", ECC on)");
+		puts(", ECC on");
 	else
-		puts(", ECC off)");
+		puts(", ECC off");
+
+	printf(", %s MHz)", strmhz(buf, gd->mem_clk));
 
 #if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
 	puts("\nSDRAM: ");
@@ -60,8 +65,6 @@ void board_add_ram_info(int use_default)
 
 #ifdef CONFIG_SPD_EEPROM
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void dma_init(void);
 extern uint dma_check(void);
@@ -78,12 +81,12 @@ extern int dma_xfer(void *dest, uint count, void *src);
 int
 picos_to_clk(int picos)
 {
-	unsigned int ddr_bus_clk;
+	unsigned int mem_bus_clk;
 	int clks;
 
-	ddr_bus_clk = gd->ddr_clk >> 1;
-	clks = picos / (1000000000 / (ddr_bus_clk / 1000));
-	if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
+	mem_bus_clk = gd->mem_clk >> 1;
+	clks = picos / (1000000000 / (mem_bus_clk / 1000));
+	if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
 		clks++;
 
 	return clks;
@@ -313,7 +316,7 @@ long int spd_sdram()
 
 	debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
 
-	ddrc_clk = gd->ddr_clk / 1000000;
+	ddrc_clk = gd->mem_clk / 1000000;
 	effective_data_rate = 0;
 
 	if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index f598699..16145dd 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -122,9 +122,9 @@ int get_clocks(void)
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
-	u32 ddr_clk;
+	u32 mem_clk;
 #if defined(CONFIG_MPC8360)
-	u32 ddr_sec_clk;
+	u32 mem_sec_clk;
 #endif
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	u32 qepmf;
@@ -400,11 +400,11 @@ int get_clocks(void)
 		return -12;
 	}
 
-	ddr_clk = csb_clk *
+	mem_clk = csb_clk *
 		  (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
 	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
 #if defined(CONFIG_MPC8360)
-	ddr_sec_clk = csb_clk * (1 +
+	mem_sec_clk = csb_clk * (1 +
 		       ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 #endif
 
@@ -466,9 +466,9 @@ int get_clocks(void)
 	gd->enc_clk = enc_clk;
 	gd->lbiu_clk = lbiu_clk;
 	gd->lclk_clk = lclk_clk;
-	gd->ddr_clk = ddr_clk;
+	gd->mem_clk = mem_clk;
 #if defined(CONFIG_MPC8360)
-	gd->ddr_sec_clk = ddr_sec_clk;
+	gd->mem_sec_clk = mem_sec_clk;
 #endif
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	gd->qe_clk = qe_clk;
@@ -508,9 +508,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #endif
 	printf("  Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
 	printf("  Local Bus:           %4d MHz\n", gd->lclk_clk / 1000000);
-	printf("  DDR:                 %4d MHz\n", gd->ddr_clk / 1000000);
+	printf("  DDR:                 %4d MHz\n", gd->mem_clk / 1000000);
 #if defined(CONFIG_MPC8360)
-	printf("  DDR Secondary:       %4d MHz\n", gd->ddr_sec_clk / 1000000);
+	printf("  DDR Secondary:       %4d MHz\n", gd->mem_sec_clk / 1000000);
 #endif
 	printf("  SEC:                 %4d MHz\n", gd->enc_clk / 1000000);
 	printf("  I2C1:                %4d MHz\n", gd->i2c1_clk / 1000000);
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 309eb30..fdf9d35 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -172,8 +172,11 @@ boot_warm: /* time t 5 */
 	/* there and deflate the flash size back to minimal size      */
 	/*------------------------------------------------------------*/
 	bl map_flash_by_law1
-	lis r4, (CFG_MONITOR_BASE)@h
-	ori r4, r4, (CFG_MONITOR_BASE)@l
+
+	GET_GOT			/* initialize GOT access	*/
+	lwz r4, GOT(_start)
+	addi r4, r4, -EXC_OFF_SYS_RESET
+
 	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr r5
 	blr
@@ -872,8 +875,8 @@ relocate_code:
 	mr	r10, r5		/* Save copy of Destination Address */
 
 	mr	r3,  r5				/* Destination Address */
-	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address */
-	ori	r4, r4, CFG_MONITOR_BASE@l
+	lwz	r4, GOT(_start)
+	addi	r4, r4, -EXC_OFF_SYS_RESET
 	lwz	r5, GOT(__init_end)
 	sub	r5, r5, r4
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size */