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| author | Kumar Gala <galak@kernel.crashing.org> | 2006-03-20 10:42:05 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2006-03-20 10:42:05 -0600 |
| commit | f8edca2e9a128f526b1fe6f997f7adb852cf5b3c (patch) | |
| tree | 92deb9ddf1153c64ff1ced9392816e60b4ecaa03 /cpu/mpc83xx/start.S | |
| parent | 79582020313e6d992a3bac71cf3a9b337f9ac7f7 (diff) | |
| parent | 7b4fd36b0322ec98836a8459d9be80e2777fdc05 (diff) | |
| download | u-boot-imx-f8edca2e9a128f526b1fe6f997f7adb852cf5b3c.zip u-boot-imx-f8edca2e9a128f526b1fe6f997f7adb852cf5b3c.tar.gz u-boot-imx-f8edca2e9a128f526b1fe6f997f7adb852cf5b3c.tar.bz2 | |
Merge branch 'origin'
Conflicts:
CHANGELOG
Diffstat (limited to 'cpu/mpc83xx/start.S')
| -rw-r--r-- | cpu/mpc83xx/start.S | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 46c748f..6e02cce 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -796,7 +796,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31 + rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr .globl dcache_enable @@ -828,7 +828,7 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31 + rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr .globl get_pvr @@ -836,6 +836,40 @@ get_pvr: mfspr r3, PVR blr +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + /*-------------------------------------------------------------------*/ /* |