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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-17 17:41:56 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-17 17:41:56 +0100 |
| commit | 0a112d8696dcffdf87a7066e2dade1eacbdd80d9 (patch) | |
| tree | 86f83dc1ad77177294d23499aadbe8db69bfdb54 /cpu/mpc83xx/start.S | |
| parent | 09e4b0c5d3881412519f33d498560a5bbcc82cd9 (diff) | |
| parent | dc9e499c620a590e0f906e807e24c85807af3338 (diff) | |
| download | u-boot-imx-0a112d8696dcffdf87a7066e2dade1eacbdd80d9.zip u-boot-imx-0a112d8696dcffdf87a7066e2dade1eacbdd80d9.tar.gz u-boot-imx-0a112d8696dcffdf87a7066e2dade1eacbdd80d9.tar.bz2 | |
Merge with port of MPC8349EMDS board
Diffstat (limited to 'cpu/mpc83xx/start.S')
| -rw-r--r-- | cpu/mpc83xx/start.S | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 46c748f..6e02cce 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -796,7 +796,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31 + rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr .globl dcache_enable @@ -828,7 +828,7 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31 + rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr .globl get_pvr @@ -836,6 +836,40 @@ get_pvr: mfspr r3, PVR blr +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + /*-------------------------------------------------------------------*/ /* |