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| author | Mike Frysinger <vapier@gentoo.org> | 2009-04-04 08:09:24 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-04-06 17:37:47 -0400 |
| commit | ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916 (patch) | |
| tree | 9b4d23d630c9aabd66271ad3e8f9859fd5f457eb /cpu/mpc83xx/speed.c | |
| parent | 51ee6e057f7a920e2a125cd9f985d10f625e355f (diff) | |
| download | u-boot-imx-ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916.zip u-boot-imx-ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916.tar.gz u-boot-imx-ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916.tar.bz2 | |
Blackfin: add workaround for anomaly 05000171
DESCRIPTION:
The Boot ROM is executed at power up/reset and changes the value of the
SICA_IWR registers from their default reset value of 0xFFFF, but does not
restore them.
WORKAROUND:
User code should not rely on the default value of these registers. Set
the desired values explicitly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu/mpc83xx/speed.c')
0 files changed, 0 insertions, 0 deletions