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| author | Kim Phillips <kim.phillips@freescale.com> | 2008-01-16 12:06:16 -0600 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-01-16 12:32:39 -0600 |
| commit | 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 (patch) | |
| tree | 82be5026f963c2fb9ce66120897c0d7b3e72dc4c /cpu/mpc83xx/speed.c | |
| parent | 711a7946277d2e29af481011e8635e9975c54e45 (diff) | |
| download | u-boot-imx-9e89647889cd4b5ada5b5e7cad6cbe55737a08d7.zip u-boot-imx-9e89647889cd4b5ada5b5e7cad6cbe55737a08d7.tar.gz u-boot-imx-9e89647889cd4b5ada5b5e7cad6cbe55737a08d7.tar.bz2 | |
mpc83xx: add support for more system clock performance controls
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).
Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com>
Signed-off by: Joe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'cpu/mpc83xx/speed.c')
| -rw-r--r-- | cpu/mpc83xx/speed.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 4f5a866..61c9379 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -367,21 +367,21 @@ int get_clocks(void) #endif #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { - case 0: + switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) { + case SCCR_SATACM_0: sata_clk = 0; break; - case 1: + case SCCR_SATACM_1: sata_clk = csb_clk; break; - case 2: + case SCCR_SATACM_2: sata_clk = csb_clk / 2; break; - case 3: + case SCCR_SATACM_3: sata_clk = csb_clk / 3; break; default: - /* unkown SCCR_SATA1CM value */ + /* unkown SCCR_SATACM value */ return -11; } #endif |