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authorMarkus Klotzbuecher <mk@denx.de>2007-05-29 16:37:57 +0200
committerMarkus Klotzbuecher <mk@pollux.denx.de>2007-05-29 16:37:57 +0200
commit51d8e813222fa3063d423220f6ff1146df58a471 (patch)
treea4951077af841bd87a90854b7fb390d12e37b851 /cpu/mpc83xx/spd_sdram.c
parent3a619dd7bed03e8b4d22a3911f90fd12af5376c2 (diff)
parent19bf91f9628f80a55d4f171df71041574882b3d6 (diff)
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Merge git://www.denx.de/git/u-boot into 2007_05_15-testing
Diffstat (limited to 'cpu/mpc83xx/spd_sdram.c')
-rw-r--r--cpu/mpc83xx/spd_sdram.c11
1 files changed, 3 insertions, 8 deletions
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753..647813f 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
int clks;
ddr_bus_clk = gd->ddr_clk >> 1;
- clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
- if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+ clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+ if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
clks++;
return clks;
@@ -624,7 +624,7 @@ long int spd_sdram()
| (1 << (16 + 10)) /* DQS Differential disable */
| (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
| (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
- | ((twr_clk >> 1) << 9) /* Write Recovery Autopre */
+ | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
| (caslat << 4) /* caslat */
| (burstlen << 0) /* Burst length */
);
@@ -693,11 +693,6 @@ long int spd_sdram()
#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
-#else
- /* SS_EN = 0, source synchronous disable
- * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
- */
- ddr->sdram_clk_cntl = 0x00000000;
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);