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authorDave Liu <daveliu@freescale.com>2006-11-03 12:11:15 -0600
committerKim Phillips <kim.phillips@freescale.com>2006-11-03 19:42:21 -0600
commit7737d5c658c606f999dfbe3e86b0fed49e5c50ef (patch)
treed1bf347ba7f4292def53870ecfcba0a1dd4c6231 /cpu/mpc83xx/cpu_init.c
parent5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 (diff)
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mpc83xx: add QE ethernet support
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
Diffstat (limited to 'cpu/mpc83xx/cpu_init.c')
-rw-r--r--cpu/mpc83xx/cpu_init.c40
1 files changed, 34 insertions, 6 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 999fe71..eb8f8c0 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -31,6 +31,30 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+ int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+ u8 port, pin;
+ int dir, open_drain, assign;
+ int i;
+
+ for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+ port = qe_iop_conf_tab[i].port;
+ pin = qe_iop_conf_tab[i].pin;
+ dir = qe_iop_conf_tab[i].dir;
+ open_drain = qe_iop_conf_tab[i].open_drain;
+ assign = qe_iop_conf_tab[i].assign;
+ qe_config_iopin(port, pin, dir, open_drain, assign);
+ }
+}
+#endif
+
/*
* Breathe some life into the CPU...
*
@@ -100,6 +124,10 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_SICRL
im->sysconf.sicrl = CFG_SICRL;
#endif
+#ifdef CONFIG_QE
+ /* Config QE ioports */
+ config_qe_ioports();
+#endif
/*
* Memory Controller:
@@ -188,12 +216,12 @@ void cpu_init_f (volatile immap_t * im)
#endif
}
-
-/*
- * Initialize higher level parts of CPU like time base and timers.
- */
-
int cpu_init_r (void)
{
+#ifdef CONFIG_QE
+ uint qe_base = CFG_IMMRBAR + 0x00100000; /* QE immr base */
+ qe_init(qe_base);
+ qe_reset();
+#endif
return 0;
}