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authorKumar Gala <galak@kernel.crashing.org>2007-02-27 23:51:42 -0600
committerKim Phillips <kim.phillips@freescale.com>2007-03-02 14:08:26 -0600
commit4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf (patch)
treee1b7ec0bc2a40f7010565599abfe3dbc90b21db9 /cpu/mpc83xx/cpu_init.c
parentd51b3cf371cd441030460ef19d36b2924c361b1a (diff)
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mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc83xx/cpu_init.c')
-rw-r--r--cpu/mpc83xx/cpu_init.c34
1 files changed, 28 insertions, 6 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index eb256e5..3ac9161 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -69,31 +69,53 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_ACR_PIPE_DEP
/* Arbiter pipeline depth */
- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
+ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
+ (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
#ifdef CFG_SPCR_TSEC1EP
/* TSEC1 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
+ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
#endif
#ifdef CFG_SPCR_TSEC2EP
/* TSEC2 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
+ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
#endif
+#ifdef CONFIG_MPC834X
#ifdef CFG_SCCR_TSEC1CM
/* TSEC1 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
+ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
#endif
#ifdef CFG_SCCR_TSEC2CM
/* TSEC2 & I2C1 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
+ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#endif
+#ifdef CFG_SCCR_USBMPHCM
+ /* USB MPH clock mode */
+ im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#endif
+#endif /* CONFIG_MPC834X */
+
+#ifdef CFG_SCCR_PCICM
+ /* PCI & DMA clock mode */
+ im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_USBDRCM
+ /* USB DR clock mode */
+ im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_ENCCM
+ /* Encryption clock mode */
+ im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
#endif
#ifdef CFG_ACR_RPTCNT
/* Arbiter repeat count */
- im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
+ im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
#endif
/* RSR - Reset Status Register - clear all status (4.6.1.3) */