* Code cleanup:

  - remove trailing white space, trailing empty lines, C++ comments, etc.
  - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)

* Patches by Kenneth Johansson, 25 Jun 2003:
  - major rework of command structure
    (work done mostly by Michal Cendrowski and Joakim Kristiansen)

1 files changed, 81 insertions, 81 deletions

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index ac77c16..b3a89f5 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -35,7 +35,7 @@
  *
  *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
  *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
- *                       
+ *
  *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
  *                              PCI Mem with prefetch
  *
@@ -44,7 +44,7 @@
  *
  *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
  *                              32-bit PCI IO
- *                      
+ *
  *   PCI->Local map (from PCI)
  *   MPC826x slave window                                  controlled by
  *
@@ -52,15 +52,15 @@
  *                              MPC826x local memory
  */
 
-/* 
- * Slave window that allows PCI masters to access MPC826x local memory. 
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
  * This window is set up using the first set of Inbound ATU registers
  */
 
-#ifndef CFG_PCI_SLV_MEM_LOCAL 
-#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */ 
-#else 
-#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL 
+#ifndef CFG_PCI_SLV_MEM_LOCAL
+#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */
+#else
+#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
 #endif
 
 #ifndef CFG_PCI_SLV_MEM_BUS
@@ -71,22 +71,22 @@
 
 #ifndef CFG_PICMR0_MASK_ATTRIB
 #define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
-                          	 PICMR_PREFETCH_EN)
+				 PICMR_PREFETCH_EN)
 #else
 #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
 #endif
 
-/* 
+/*
  * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI 
- * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
  * these windows.
  */
 
 /* PCIBR0 */
 #ifndef CFG_PCI_MSTR0_LOCAL
-#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */ 
-#else 
+#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#else
 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
 #endif
 
@@ -98,9 +98,9 @@
 
 /* PCIBR1 */
 #ifndef CFG_PCI_MSTR1_LOCAL
-#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */ 
-#else 
-#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL 
+#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#else
+#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL
 #endif
 
 #ifndef CFG_PCIMSK1_MASK
@@ -109,7 +109,7 @@
 #define  PCIMSK1_MASK		CFG_PCIMSK1_MASK
 #endif
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (prefetch).
  * This window will be setup with the first set of Outbound ATU registers
  * in the bridge.
@@ -145,34 +145,34 @@
 #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
 #endif
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
  * This window will be setup with the second set of Outbound ATU registers
  * in the bridge.
  */
 
-#ifndef CFG_PCI_MSTR_MEMIO_LOCAL 
-#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */ 
-#else 
-#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL 
+#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
+#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */
+#else
+#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
 #endif
 
-#ifndef CFG_PCI_MSTR_MEMIO_BUS 
-#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */ 
-#else 
-#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS 
+#ifndef CFG_PCI_MSTR_MEMIO_BUS
+#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */
+#else
+#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
 #endif
 
-#ifndef CFG_CPU_PCI_MEMIO_START 
-#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 
-#else 
-#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START 
+#ifndef CFG_CPU_PCI_MEMIO_START
+#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#else
+#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
 #endif
 
-#ifndef CFG_PCI_MSTR_MEMIO_SIZE 
-#define PCI_MSTR_MEMIO_SIZE 0x10000000          /* 256 MB */ 
-#else 
-#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE 
+#ifndef CFG_PCI_MSTR_MEMIO_SIZE
+#define PCI_MSTR_MEMIO_SIZE 0x10000000          /* 256 MB */
+#else
+#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
 #endif
 
 #ifndef CFG_POCMR1_MASK_ATTRIB
@@ -181,34 +181,34 @@
 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
 #endif
 
-/* 
+/*
  * Master window that allows the CPU to access PCI IO space.
  * This window will be setup with the third set of Outbound ATU registers
  * in the bridge.
  */
 
-#ifndef CFG_PCI_MSTR_IO_LOCAL 
-#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */ 
-#else 
-#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL 
+#ifndef CFG_PCI_MSTR_IO_LOCAL
+#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */
+#else
+#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
 #endif
 
-#ifndef CFG_PCI_MSTR_IO_BUS 
-#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */ 
-#else 
-#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS 
+#ifndef CFG_PCI_MSTR_IO_BUS
+#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */
+#else
+#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
 #endif
 
-#ifndef CFG_CPU_PCI_IO_START 
-#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 
-#else 
-#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START 
+#ifndef CFG_CPU_PCI_IO_START
+#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#else
+#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
 #endif
 
-#ifndef CFG_PCI_MSTR_IO_SIZE 
-#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */ 
-#else 
-#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE 
+#ifndef CFG_PCI_MSTR_IO_SIZE
+#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */
+#else
+#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
 #endif
 
 #ifndef CFG_POCMR2_MASK_ATTRIB
@@ -239,7 +239,7 @@ void pci_mpc8250_init(struct pci_controller *hose)
     pci_dev_t host_devno = PCI_BDF(0, 0, 0);
 
     pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
-	                         CFG_IMMR + PCI_CFG_DATA_REG);
+				 CFG_IMMR + PCI_CFG_DATA_REG);
 
     /*
      * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
@@ -248,23 +248,23 @@ void pci_mpc8250_init(struct pci_controller *hose)
     immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 				   | SIUMCR_LBPC01;
 #else
-    /* 
-     * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 
+    /*
+     * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
      * and local bus for PCI (SIUMCR [LBPC]).
      */
-    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & 
-						  ~SIUMCR_LBPC11 & 
-						~SIUMCR_CS10PC11 & 
+    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+						  ~SIUMCR_LBPC11 &
+						~SIUMCR_CS10PC11 &
 						 ~SIUMCR_LBPC11) |
-				   SIUMCR_LBPC01 | 
-				   SIUMCR_CS10PC01 | 
+				   SIUMCR_LBPC01 |
+				   SIUMCR_CS10PC01 |
 				   SIUMCR_LBPC01;
 #endif
 
     /* Make PCI lowest priority */
-    /* Each 4 bits is a device bus request  and the MS 4bits 
+    /* Each 4 bits is a device bus request  and the MS 4bits
        is highest priority */
-    /* Bus               4bit value 
+    /* Bus               4bit value
 	   ---               ----------
        CPM high          0b0000
        CPM middle        0b0001
@@ -282,8 +282,8 @@ void pci_mpc8250_init(struct pci_controller *hose)
     /* Park bus on core while modifying PCI Bus accesses */
     immap->im_siu_conf.sc_ppc_acr = 0x6;
 
-    /* 
-     * Set up master windows that allow the CPU to access PCI space. These 
+    /*
+     * Set up master windows that allow the CPU to access PCI space. These
      * windows are set up using the two SIU PCIBR registers.
      */
     *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
@@ -294,40 +294,40 @@ void pci_mpc8250_init(struct pci_controller *hose)
     *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
     *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
 	    PCI_MSTR1_LOCAL | PCIBR_ENABLE;
-#endif 
+#endif
 
     /* Release PCI RST (by default the PCI RST signal is held low)  */
     pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
 
     /* give it some time */
     {
-#ifdef CONFIG_MPC8266ADS 
-		/* Give the PCI cards more time to initialize before query 
+#ifdef CONFIG_MPC8266ADS
+		/* Give the PCI cards more time to initialize before query
 			This might be good for other boards also
 		*/
-        int i;
-        for (i = 0; i < 1000; ++i)
+	int i;
+	for (i = 0; i < 1000; ++i)
 #endif
-            udelay(1000);
+	    udelay(1000);
     }
 
-    /* 
-     * Set up master window that allows the CPU to access PCI Memory (prefetch) 
+    /*
+     * Set up master window that allows the CPU to access PCI Memory (prefetch)
      * space. This window is set up using the first set of Outbound ATU registers.
      */
     pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12);      /* PCI base */
     pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12);    /* Local base */
     pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB);    /* Size & attribute */
 
-    /* 
-     * Set up master window that allows the CPU to access PCI Memory (non-prefetch) 
+    /*
+     * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
      * space. This window is set up using the second set of Outbound ATU registers.
      */
     pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12);    /* PCI base */
     pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12);  /* Local base */
     pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB);    /* Size & attribute */
-    
-    /* 
+
+    /*
      * Set up master window that allows the CPU to access PCI IO space. This window
      * is set up using the third set of Outbound ATU registers.
      */
@@ -335,8 +335,8 @@ void pci_mpc8250_init(struct pci_controller *hose)
     pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12);     /* Local base */
     pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB);    /* Size & attribute */
 
-    /* 
-     * Set up slave window that allows PCI masters to access MPC826x local memory. 
+    /*
+     * Set up slave window that allows PCI masters to access MPC826x local memory.
      * This window is set up using the first set of Inbound ATU registers
      */
     pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12);     /* Local base */
@@ -352,18 +352,18 @@ void pci_mpc8250_init(struct pci_controller *hose)
     /* Host mode - specify the bridge as a host-PCI bridge */
 
     pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
-	                           PCI_CLASS_BRIDGE_CTLR);
+				   PCI_CLASS_BRIDGE_CTLR);
 
     /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
     pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
     pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
-		         tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+			 tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 
 #ifdef CONFIG_MPC8266ADS
 	/* do some bridge init, should be done on all 8260 based bridges */
 	pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08);
 	pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8);
-#endif 
+#endif
 
     hose->first_busno = 0;
     hose->last_busno = 0xff;