Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 63 insertions, 14 deletions

diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index c3af7b6..a934193 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -36,6 +36,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_I2C_MULTI_BUS)
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#endif /* CONFIG_I2C_MULTI_BUS */
+
 /* uSec to wait between polls of the i2c */
 #define DELAY_US	100
 /* uSec to wait for the CPM to start processing the buffer */
@@ -50,12 +54,12 @@ DECLARE_GLOBAL_DATA_PTR;
 /*-----------------------------------------------------------------------
  * Set default values
  */
-#ifndef	CFG_I2C_SPEED
-#define	CFG_I2C_SPEED	50000
+#ifndef	CONFIG_SYS_I2C_SPEED
+#define	CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef	CFG_I2C_SLAVE
-#define	CFG_I2C_SLAVE	0xFE
+#ifndef	CONFIG_SYS_I2C_SLAVE
+#define	CONFIG_SYS_I2C_SLAVE	0xFE
 #endif
 /*-----------------------------------------------------------------------
  */
@@ -172,7 +176,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval,
  */
 static int i2c_setrate(int hz, int speed)
 {
-    immap_t	*immap = (immap_t *)CFG_IMMR ;
+    immap_t	*immap = (immap_t *)CONFIG_SYS_IMMR ;
     volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
     int brgval,
 	  modval,	/* 0-3 */
@@ -215,7 +219,7 @@ static int i2c_setrate(int hz, int speed)
 
 void i2c_init(int speed, int slaveadd)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 	volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 	volatile iic_t *iip;
@@ -223,7 +227,7 @@ void i2c_init(int speed, int slaveadd)
 	volatile I2C_BD *rxbd, *txbd;
 	uint dpaddr;
 
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
 	/* environment, which might be in a chip on that bus. For details   */
 	/* about this problem see doc/I2C_Edge_Conditions.                  */
@@ -266,7 +270,7 @@ void i2c_init(int speed, int slaveadd)
 	 * divide BRGCLK by 1)
 	 */
 	PRINTD(("[I2C] Setting rate...\n"));
-	i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ;
+	i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
 
 	/* Set I2C controller in master mode */
 	i2c->i2c_i2com = 0x01;
@@ -305,7 +309,7 @@ void i2c_init(int speed, int slaveadd)
 static
 void i2c_newio(i2c_state_t *state)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 	volatile iic_t *iip;
 	uint dpaddr;
 
@@ -490,7 +494,7 @@ int i2c_receive(i2c_state_t *state,
 static
 int i2c_doio(i2c_state_t *state)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 	volatile iic_t *iip;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 	volatile I2C_BD *txbd, *rxbd;
@@ -663,7 +667,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	xaddr[2] = (addr >>  8) & 0xFF;
 	xaddr[3] =  addr        & 0xFF;
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	 /*
 	  * EEPROM chips that implement "address overflow" are ones
 	  * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
@@ -675,7 +679,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	  * be one byte because the extra address bits are hidden in the
 	  * chip address.
 	  */
-	chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
 	i2c_newio(&state);
@@ -712,7 +716,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	xaddr[2] = (addr >>  8) & 0xFF;
 	xaddr[3] =  addr        & 0xFF;
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	 /*
 	  * EEPROM chips that implement "address overflow" are ones
 	  * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
@@ -724,7 +728,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	  * be one byte because the extra address bits are hidden in the
 	  * chip address.
 	  */
-	chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
 	i2c_newio(&state);
@@ -765,4 +769,49 @@ i2c_reg_write(uchar chip, uchar reg, uchar val)
 	i2c_write(chip, reg, 1, &val, 1);
 }
 
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * Functions for multiple I2C bus handling
+ */
+unsigned int i2c_get_bus_num(void)
+{
+	return i2c_bus_num;
+}
+
+int i2c_set_bus_num(unsigned int bus)
+{
+#if defined(CONFIG_I2C_MUX)
+	if (bus < CONFIG_SYS_MAX_I2C_BUS) {
+		i2c_bus_num = bus;
+	} else {
+		int	ret;
+
+		ret = i2x_mux_select_mux(bus);
+		if (ret == 0)
+			i2c_bus_num = bus;
+		else
+			return ret;
+	}
+#else
+	if (bus >= CONFIG_SYS_MAX_I2C_BUS)
+		return -1;
+	i2c_bus_num = bus;
+#endif
+	return 0;
+}
+/* TODO: add 100/400k switching */
+unsigned int i2c_get_bus_speed(void)
+{
+	return CONFIG_SYS_I2C_SPEED;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+	if (speed != CONFIG_SYS_I2C_SPEED)
+		return -1;
+
+	return 0;
+}
+
+#endif	/* CONFIG_I2C_MULTI_BUS */
 #endif	/* CONFIG_HARD_I2C */