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author | Heiko Schocher <hs@pollux.denx.de> | 2007-03-21 08:45:17 +0100 |
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committer | Heiko Schocher <hs@pollux.denx.de> | 2007-03-21 08:45:17 +0100 |
commit | 07e82cb2e284a893df6693f2a1337ab2c47bf6a1 (patch) | |
tree | 4ba9f6b0c706b16cd7900954e1cd44800abb9699 /cpu/mpc8260/cpu_init.c | |
parent | 87e0662762b78ed7731f14add60ba0edb0479252 (diff) | |
download | u-boot-imx-07e82cb2e284a893df6693f2a1337ab2c47bf6a1.zip u-boot-imx-07e82cb2e284a893df6693f2a1337ab2c47bf6a1.tar.gz u-boot-imx-07e82cb2e284a893df6693f2a1337ab2c47bf6a1.tar.bz2 |
[PATCH] TQM8272: dont change the bits given from the HRCW
for the SIUMCR and BCR Register.
Fix the calculation for the EEprom Size
Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'cpu/mpc8260/cpu_init.c')
-rw-r--r-- | cpu/mpc8260/cpu_init.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 7dcc949..380d7af 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -129,9 +129,9 @@ void cpu_init_f (volatile immap_t * immr) /* BCR - Bus Configuration Register (4-25) */ #if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE) if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = CFG_BCR_60x; + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010); } else { - immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE; + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010); } #else immr->im_siu_conf.sc_bcr = CFG_BCR; @@ -141,9 +141,9 @@ void cpu_init_f (volatile immap_t * immr) #if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH) cpu_clk = board_get_cpu_clk_f (); if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH; + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000); } else { - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW; + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000); } #else immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; |