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| author | wdenk <wdenk> | 2003-09-10 22:30:53 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-09-10 22:30:53 +0000 |
| commit | 7205e4075d8b50e4dd89fe39ed03860b23cbb704 (patch) | |
| tree | 0dfa865e7087ff4ee07967a2531c91ff5645a802 /cpu/mpc824x/start.S | |
| parent | 149dded2b178bc0fb62cb6f61b87968d914b580a (diff) | |
| download | u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.zip u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.gz u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.bz2 | |
* Patches by Denis Peter, 9 Sep 2003:
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
Diffstat (limited to 'cpu/mpc824x/start.S')
| -rw-r--r-- | cpu/mpc824x/start.S | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index a22137c..9ff052c 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -526,11 +526,26 @@ relocate_code: stwu r0,-4(r7) bdnz 3b +4: +#if !defined(CONFIG_BMW) +/* Unlock the data cache and invalidate locked area */ + xor r0, r0, r0 + mtspr 1011, r0 + lis r4, CFG_INIT_RAM_ADDR@h + ori r4, r4, CFG_INIT_RAM_ADDR@l + li r0, 128 + mtctr r0 +41: + dcbi r0, r4 + addi r4, r4, 32 + bdnz 41b +#endif + /* * Now flush the cache: note that we must start from a cache aligned * address. Otherwise we might miss one cache line. */ -4: cmpwi r6,0 + cmpwi r6,0 add r5,r3,r5 beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 |