* Code cleanup:

  - remove trailing white space, trailing empty lines, C++ comments, etc.
  - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)

* Patches by Kenneth Johansson, 25 Jun 2003:
  - major rework of command structure
    (work done mostly by Michal Cendrowski and Joakim Kristiansen)

20 files changed, 265 insertions, 284 deletions

diff --git a/cpu/mpc824x/drivers/dma/README b/cpu/mpc824x/drivers/dma/README
index ab4b68b..06f4bc0 100644
--- a/cpu/mpc824x/drivers/dma/README
+++ b/cpu/mpc824x/drivers/dma/README
@@ -98,5 +98,3 @@ USAGE:
 7. The DMA driver routines contains a set
    of utilities, Set and Get, for host system
    to query and modify the desired DMA registers.
-
-
diff --git a/cpu/mpc824x/drivers/dma/dma1.c b/cpu/mpc824x/drivers/dma/dma1.c
index 8c3834e..9c85267 100644
--- a/cpu/mpc824x/drivers/dma/dma1.c
+++ b/cpu/mpc824x/drivers/dma/dma1.c
@@ -129,12 +129,12 @@ DMA_Status DMA_Initialize( int (*p)(char *,...))
  * snoop is the snoop enable control
  */
 extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
-                                       DMA_TRANSFER_TYPE type,
-                                       unsigned int source,
-                                       unsigned int dest,
-                                       unsigned int len,
-                                       DMA_CHANNEL channel,
-                                       DMA_SNOOP_MODE snoop)
+				       DMA_TRANSFER_TYPE type,
+				       unsigned int source,
+				       unsigned int dest,
+				       unsigned int len,
+				       DMA_CHANNEL channel,
+				       DMA_SNOOP_MODE snoop)
 {
     DMA_MR md;
     DMA_CDAR cdar;
@@ -755,7 +755,7 @@ DMAStatus DMA_ISR( unsigned int eumbbar,
 	}
 	else if ( stat.pe == 1 )
 	{
-        /* PCI error */
+	/* PCI error */
 		rval = DMAPERROR;
 		if ( pe_func != 0 )
 		{
@@ -783,7 +783,7 @@ DMAStatus DMA_ISR( unsigned int eumbbar,
 	}
 
     temp = ( stat.reserved0 & 0xffffff ) << 8;
-   	temp |= ( ( stat.lme       & 0x1 ) << 7 );  /* write one to clear */
+	temp |= ( ( stat.lme       & 0x1 ) << 7 );  /* write one to clear */
 	temp |= ( ( stat.reserved1 & 0x3 ) << 5 );
     temp |= ( ( stat.pe        & 0x1 ) << 4 );  /* write one to clear */
     temp |= ( ( stat.reserved2 & 0x1 ) << 3 );
diff --git a/cpu/mpc824x/drivers/dma/dma2.S b/cpu/mpc824x/drivers/dma/dma2.S
index dab1de3..ccbc226 100644
--- a/cpu/mpc824x/drivers/dma/dma2.S
+++ b/cpu/mpc824x/drivers/dma/dma2.S
@@ -12,16 +12,16 @@
  *
  * output: r3 - register content
  **********************************************************/
-      .text
-      .align 2
-      .global load_runtime_reg
+	.text
+	.align 2
+	.global load_runtime_reg
 
 load_runtime_reg:
 
-	      lwbrx	r3,r4,r3
-	      sync
+	lwbrx	r3,r4,r3
+	sync
 
- 	      bclr 20, 0
+	bclr 20, 0
 
 /****************************************************************
  * function: store_runtime_reg
@@ -31,15 +31,12 @@ load_runtime_reg:
  *        r5 - new value to be stored
  *
  ****************************************************************/
-           .text
-           .align 2
-           .global store_runtime_reg
+	.text
+	.align 2
+	.global store_runtime_reg
 store_runtime_reg:
 
-	      stwbrx r5,  r4, r3
-	      sync
-
-		  bclr   20,0
-
-
+	stwbrx r5,  r4, r3
+	sync
 
+	bclr   20,0
diff --git a/cpu/mpc824x/drivers/dma/dma_export.h b/cpu/mpc824x/drivers/dma/dma_export.h
index cb750dd..471e488 100644
--- a/cpu/mpc824x/drivers/dma/dma_export.h
+++ b/cpu/mpc824x/drivers/dma/dma_export.h
@@ -71,9 +71,9 @@ typedef enum _dma_snoop_mode
  *  This function must be called before DMA unit can be used.
  */
 extern DMA_Status DMA_Initialize(
-        int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-                                                 * provided by application
-                                                 */
+	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+						 * provided by application
+						 */
 
 /* Perform the DMA transfer, only direct mode is currently implemented.
  * At this point, I think it would be better to define a different
@@ -91,10 +91,10 @@ extern DMA_Status DMA_Initialize(
  * snoop is the snoop enable control
  */
 extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
-                                       DMA_TRANSFER_TYPE type,
-                                       unsigned int source,
-                                       unsigned int dest,
-                                       unsigned int len,
-                                       DMA_CHANNEL channel,
-                                       DMA_SNOOP_MODE snoop);
+				       DMA_TRANSFER_TYPE type,
+				       unsigned int source,
+				       unsigned int dest,
+				       unsigned int len,
+				       DMA_CHANNEL channel,
+				       DMA_SNOOP_MODE snoop);
 #endif
diff --git a/cpu/mpc824x/drivers/dma_export.h b/cpu/mpc824x/drivers/dma_export.h
index cb750dd..471e488 100644
--- a/cpu/mpc824x/drivers/dma_export.h
+++ b/cpu/mpc824x/drivers/dma_export.h
@@ -71,9 +71,9 @@ typedef enum _dma_snoop_mode
  *  This function must be called before DMA unit can be used.
  */
 extern DMA_Status DMA_Initialize(
-        int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-                                                 * provided by application
-                                                 */
+	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+						 * provided by application
+						 */
 
 /* Perform the DMA transfer, only direct mode is currently implemented.
  * At this point, I think it would be better to define a different
@@ -91,10 +91,10 @@ extern DMA_Status DMA_Initialize(
  * snoop is the snoop enable control
  */
 extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
-                                       DMA_TRANSFER_TYPE type,
-                                       unsigned int source,
-                                       unsigned int dest,
-                                       unsigned int len,
-                                       DMA_CHANNEL channel,
-                                       DMA_SNOOP_MODE snoop);
+				       DMA_TRANSFER_TYPE type,
+				       unsigned int source,
+				       unsigned int dest,
+				       unsigned int len,
+				       DMA_CHANNEL channel,
+				       DMA_SNOOP_MODE snoop);
 #endif
diff --git a/cpu/mpc824x/drivers/epic/README b/cpu/mpc824x/drivers/epic/README
index ae95b88..5798996 100644
--- a/cpu/mpc824x/drivers/epic/README
+++ b/cpu/mpc824x/drivers/epic/README
@@ -100,5 +100,3 @@ USAGE:
    shall always call the epicEOI just before
    rfi instruction. Refer to the routine,
    epic_exception, for a code sample.
-
-
diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h
index 17e4afb..58f81c5 100644
--- a/cpu/mpc824x/drivers/epic/epic.h
+++ b/cpu/mpc824x/drivers/epic/epic.h
@@ -123,7 +123,7 @@ void epicVendorId( unsigned int *step,
        unsigned int *venId
      );
 void epicFeatures( unsigned int *noIRQs,
-             unsigned int *noCPUs,
+	     unsigned int *noCPUs,
        unsigned int *VerId );
 extern void epicInit( unsigned int IRQType, unsigned int clkRatio);
 ULONG sysEUMBBARRead ( ULONG regNum );
@@ -131,8 +131,8 @@ void sysEUMBBARWrite ( ULONG regNum, ULONG regVal);
 extern void epicTmFrequencySet( unsigned int frq );
 extern unsigned int epicTmFrequencyGet(void);
 extern unsigned int epicTmBaseSet( ULONG srcAddr,
-                 unsigned int cnt,
-                 unsigned int inhibit );
+		 unsigned int cnt,
+		 unsigned int inhibit );
 extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val );
 extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val );
 extern unsigned int epicTmInhibit( unsigned int timer );
@@ -144,7 +144,7 @@ extern void epicIntTaskSet( unsigned char val );
 extern unsigned int epicIntAck(void);
 extern void epicSprSet( unsigned int eumbbar, unsigned char );
 extern void epicConfigGet( unsigned int *clkRatio,
-               unsigned int *serEnable );
+	       unsigned int *serEnable );
 extern void SrcVecTableInit(void);
 extern unsigned int  epicModeGet(void);
 extern void epicIntEnable(int Vect);
diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c
index eb7ed40..f89deed 100644
--- a/cpu/mpc824x/drivers/epic/epic1.c
+++ b/cpu/mpc824x/drivers/epic/epic1.c
@@ -78,12 +78,12 @@ void epicInit
     tmp = sysEUMBBARRead(EPIC_INT_CONF_REG);    /* Read interrupt conf. reg */
 
     if (IRQType == EPIC_DIRECT_IRQ)             /* direct mode */
-        sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
+	sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
     else                                        /* Serial mode */
-        {
-        tmp = (clkRatio << 28) | 0x08000000;    /* Set clock ratio */
-        sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
-        }
+	{
+	tmp = (clkRatio << 28) | 0x08000000;    /* Set clock ratio */
+	sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
+	}
 
     while (epicIntAck() != 0xff)       /* Clear all pending interrupts */
 		epicEOI();
@@ -168,7 +168,7 @@ int epicIntSourceConfig
     tmp = sysEUMBBARRead(srAddr);
     actBit = (tmp & 40000000) >> 30;    /* retrieve activity bit - bit 30 */
     if (actBit == 1)
-        return ERROR;
+	return ERROR;
 
     tmp &= 0xff30ff00;     /* Erase previously set P,S,Prio,Vector bits */
     newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect;
@@ -220,7 +220,7 @@ int epicCurTaskPrioSet
     {
 
     if ( (prioNum < 0) || (prioNum > 0xF))
-        return ERROR;
+	return ERROR;
     sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum);
     return OK;
     }
@@ -465,7 +465,6 @@ unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val )
 }
 
 
-
 /***********************************************************
  * function: epicTmInhibit
  *
diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S
index 8979f88..8cc2fc6 100644
--- a/cpu/mpc824x/drivers/epic/epic2.S
+++ b/cpu/mpc824x/drivers/epic/epic2.S
@@ -17,14 +17,14 @@
  **********************************************/
 		.text
 		.align 2
-        .global CoreExtIntEnable
+	.global CoreExtIntEnable
 CoreExtIntEnable:
-         mfmsr    r3
+	 mfmsr    r3
 
-         ori      r3,r3,0x8000         /* enable external interrupt */
-         mtmsr    r3
+	 ori      r3,r3,0x8000         /* enable external interrupt */
+	 mtmsr    r3
 
-         bclr 20, 0
+	 bclr 20, 0
 
 /*******************************************
  * function: CoreExtIntDisable
@@ -35,20 +35,20 @@ CoreExtIntEnable:
  *******************************************/
 		.text
 		.align 2
-        .global CoreExtIntDisable
+	.global CoreExtIntDisable
 CoreExtIntDisable:
-        mfmsr    r4
+	mfmsr    r4
 
 	xor	r3,r3,r3
 	or      r3,r3,r4
 
 	andis.	r4,r4,0xffff
-        andi.   r3,r3,0x7fff         /* disable external interrupt */
+	andi.   r3,r3,0x7fff         /* disable external interrupt */
 
 	or      r3,r3,r4
-        mtmsr    r3
+	mtmsr    r3
 
-        bclr 20, 0
+	bclr 20, 0
 
 /*********************************************************
  * function: epicEOI
@@ -61,20 +61,20 @@ CoreExtIntDisable:
  ********************************************************/
 		.text
 		.align 2
-        .global epicEOI
+	.global epicEOI
 epicEOI:
 	lis	r5,0x0006	        /* Build End Of Interrupt Register offset */
 	ori	r5,r5,0x00b0
 	xor	r7,r7,r7	        /* Clear r7 */
 	stwbrx	r7,r5,r3	    /* Save r7, writing to this register will
-				             * intidate the end of processing the
-	 			             * highest interrupt.
-                             */
+					     * intidate the end of processing the
+					     * highest interrupt.
+			     */
 	sync
 
 	/* ---RESTORE MACHINE STATE */
 	mfmsr	r13		        /* Clear Recoverable Interrupt bit in MSR */
-        or      r7,r7,r13
+	or      r7,r7,r13
 
 	andis.  r7,r7,0xffff
 	andi.	r13,r13,0x7ffd	/* (and disable interrupts) */
@@ -147,8 +147,8 @@ epic_exception:
 	stw     r3,0x1c(r1) /* Push CTR */
 
 	mtspr	SPRG0,r1	/* Save updated Supervisor stack pointer
-				         * value to SPRG0
-                         */
+					 * value to SPRG0
+			 */
 	mfmsr	r3
 	ori	    r3,r3,0x0002	/* Set Recoverable Interrupt bit in MSR */
 	mtmsr	r3
@@ -159,8 +159,8 @@ epic_exception:
 
 	/* ---READ EPIC REGISTER:	PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */
 	lis	r5,0x0006	        /* Build Interrupt Acknowledge Register
-				             * offset
-                             */
+					     * offset
+			     */
 	ori	r5,r5,0x00a0
 	lwbrx	r7,r5,r6    /* Load interrupt vector into r7 */
 	sync
diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/cpu/mpc824x/drivers/epic/epicutil.S
index a83fbd8..4877050 100644
--- a/cpu/mpc824x/drivers/epic/epicutil.S
+++ b/cpu/mpc824x/drivers/epic/epicutil.S
@@ -29,12 +29,12 @@
 load_runtime_reg:
 
 		  xor r5,r5,r5
-          or  r5,r5,r3       /* save eumbbar */
+	  or  r5,r5,r3       /* save eumbbar */
 
 	      lwbrx	r3,r4,r5
 	      sync
 
- 	      bclr 20, 0
+	      bclr 20, 0
 
 /****************************************************************
  * function: store_runtime_reg
@@ -44,9 +44,9 @@ load_runtime_reg:
  *        r5 - new value to be stored
  *
  ****************************************************************/
-           .text
-           .align 2
-           .global store_runtime_reg
+	   .text
+	   .align 2
+	   .global store_runtime_reg
 store_runtime_reg:
 
 		  xor r0,r0,r0
@@ -55,4 +55,3 @@ store_runtime_reg:
 	      sync
 
 		  bclr   20,0
-
diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h
index 1435188..887f284 100644
--- a/cpu/mpc824x/drivers/errors.h
+++ b/cpu/mpc824x/drivers/errors.h
@@ -30,7 +30,7 @@
 #include "config.h"
 
 /*
-         1         2         3         4         5         6         7         8
+	 1         2         3         4         5         6         7         8
 01234567890123456789012345678901234567890123456789012345678901234567890123456789
 */
 /* List define statements here */
@@ -78,7 +78,6 @@ to standardize the error handling in the current project */
 #define FOR_BOARD_ONLY		0xfb0a  /* "Not available for Unix." */
 
 
-
 /*----------------------------------------------------------------------*/
 /* these are for the error checking toolbox				*/
 
@@ -147,9 +146,6 @@ to standardize the error handling in the current project */
 #define UNKNOWN_PARAMETER	0xFE01 /* "unknown type of parameter "*/
 
 
-
-
-
 /*----------------------------------------------------------------------*/
 /* these are for the tokenizer toolbox 					*/
 
@@ -164,7 +160,6 @@ to standardize the error handling in the current project */
 #define NO_OPEN_IBS		0xFF08 /* "no open input buffers" */
 
 
-
 /* these are for the read from screen toolbox */
 
 #define RESERVED_WORD		0xFC00 /* used a reserved word as an arguement*/
@@ -175,7 +170,6 @@ to standardize the error handling in the current project */
 #define FULL_BPDS		0xFA00 /* breakpoint data structure is full */
 
 
-
 /* THESE are for the downloader */
 
 #define NOT_IN_S_RECORD_FORMAT 	0xf900 /* "not in S-Record Format" */
diff --git a/cpu/mpc824x/drivers/i2c/README b/cpu/mpc824x/drivers/i2c/README
index 8d82df3..1db7210 100644
--- a/cpu/mpc824x/drivers/i2c/README
+++ b/cpu/mpc824x/drivers/i2c/README
@@ -102,4 +102,3 @@ USAGE:
    host system a way to use its own event
    handler instead of the I2C_ISR provided
    here.
-
diff --git a/cpu/mpc824x/drivers/i2c/i2c.h b/cpu/mpc824x/drivers/i2c/i2c.h
index 3209bfe..48a401d 100644
--- a/cpu/mpc824x/drivers/i2c/i2c.h
+++ b/cpu/mpc824x/drivers/i2c/i2c.h
@@ -109,13 +109,13 @@ typedef enum _i2c_mode
  */
 static I2CStatus I2C_put( unsigned int  eumbbar,
 						  unsigned char rcv_addr,    /* receiver's address */
-	                      unsigned char *buffer_ptr, /* pointer of data to be sent */
+			      unsigned char *buffer_ptr, /* pointer of data to be sent */
 					      unsigned int  length,      /* number of byte of in the buffer */
 					      unsigned int  stop_flag,   /* 1 - signal STOP when buffer is empty
-					                                  * 0 - no STOP signal when buffer is empty
-											          */
+									  * 0 - no STOP signal when buffer is empty
+												  */
 						  unsigned int  is_cnt );    /* 1 - this is a restart, don't check MBB
-                                                      * 0 - this is a new start, check MBB
+						      * 0 - this is a new start, check MBB
 													  */
 
 /* Receive a buffer of data from the desired sender_addr
@@ -130,12 +130,12 @@ static I2CStatus I2C_put( unsigned int  eumbbar,
 static I2CStatus I2C_get( unsigned int  eumbbar,
 						  unsigned char sender_addr, /* sender's address */
 					      unsigned char *buffer_ptr, /* pointer of receiving buffer */
-				          unsigned int  length,      /* length of the receiving buffer */
+					  unsigned int  length,      /* length of the receiving buffer */
 					      unsigned int  stop_flag,   /* 1 - signal STOP when buffer is full
-					                                  * 0 - no STOP signal when buffer is full
+									  * 0 - no STOP signal when buffer is full
 												      */
 						  unsigned int  is_cnt );    /* 1 - this is a restart, don't check MBB
-                                                      * 0 - this is a new start, check MBB
+						      * 0 - this is a new start, check MBB
 													  */
 
 #if 0 /* the I2C_write and I2C_read functions are not active */
@@ -160,10 +160,10 @@ static I2CStatus I2C_get( unsigned int  eumbbar,
  */
 static I2CStatus I2C_write( unsigned int eumbbar,
 						    unsigned char *buffer_ptr, /* pointer of data to be sent */
-					        unsigned int  length,      /* number of byte of in the buffer */
-					        unsigned int  stop_flag ); /* 1 - signal STOP when buffer is empty
-								                        * 0 - no STOP signal when buffer is empty
-											            */
+						unsigned int  length,      /* number of byte of in the buffer */
+						unsigned int  stop_flag ); /* 1 - signal STOP when buffer is empty
+											* 0 - no STOP signal when buffer is empty
+												    */
 
  /* Receive a buffer of data from the sending master.
  * If stop_flag is set, when the buffer is full and the
@@ -175,8 +175,8 @@ static I2CStatus I2C_write( unsigned int eumbbar,
 static I2CStatus I2C_read(unsigned int  eumbbar,
 						  unsigned char *buffer_ptr, /* pointer of receiving buffer */
 					      unsigned int  length,      /* length of the receiving buffer */
-				          unsigned int  stop_flag ); /* 1 - signal STOP when buffer is full
-					                                  * 0 - no STOP signal when buffer is full
+					  unsigned int  stop_flag ); /* 1 - signal STOP when buffer is full
+									  * 0 - no STOP signal when buffer is full
 												      */
 #endif /* of if0 for turning off I2C_read & I2C_write */
 
@@ -203,12 +203,12 @@ static I2CStatus I2C_Timer_Event( unsigned int eumbbar, I2CStatus (*handler)( un
  */
 static I2CStatus I2C_Start( unsigned int  eumbbar,
 						    unsigned char slave_addr, /* address of the receiver */
-	                        I2C_MODE     mode,       /* XMIT(1) - put (write)
-							                          * RCV(0)  - get (read)
+				I2C_MODE     mode,       /* XMIT(1) - put (write)
+										  * RCV(0)  - get (read)
 													  */
 						    unsigned int is_cnt ); /* 1 - this is a restart, don't check MBB
 													* 0 - this is a new start, check MBB
-                                                    */
+						    */
 
 /* Generate a STOP signal to terminate the transaction. */
 static I2CStatus I2C_Stop( unsigned int eumbbar );
@@ -258,10 +258,10 @@ static I2CStatus I2C_Slave_Addr( unsigned int eumbbar );
  */
 static I2CStatus I2C_Init( unsigned int  eumbbar,
 						   unsigned char fdr,       /* frequency divider */
-	                       unsigned char addr,      /* driver's address used for receiving */
-	 			           unsigned int en_int);    /* 1 - enable I2C interrupt
-					                                 * 0 - disable I2C interrup
-											         */
+			       unsigned char addr,      /* driver's address used for receiving */
+					   unsigned int en_int);    /* 1 - enable I2C interrupt
+									 * 0 - disable I2C interrup
+												 */
 
 /* I2C interrupt service routine.
  *
@@ -299,11 +299,11 @@ static I2C_CTRL I2C_Get_Ctrl( unsigned int eumbbar );
  *        I2C_RESTART, this is a continuation of existing transaction
  */
 static I2C_Status I2C_do_buffer( I2C_INTERRUPT_MODE en_int,
-                                 I2C_TRANSACTION_MODE act,
-                                 unsigned char i2c_addr,
-                                 int len,
-                                 unsigned char *buffer,
-                                 I2C_STOP_MODE stop,
-                                 int retry,
-                                 I2C_RESTART_MODE rsta);
+				 I2C_TRANSACTION_MODE act,
+				 unsigned char i2c_addr,
+				 int len,
+				 unsigned char *buffer,
+				 I2C_STOP_MODE stop,
+				 int retry,
+				 I2C_RESTART_MODE rsta);
 #endif
diff --git a/cpu/mpc824x/drivers/i2c/i2c2.S b/cpu/mpc824x/drivers/i2c/i2c2.S
index 5cc7c98..3fd7e03 100644
--- a/cpu/mpc824x/drivers/i2c/i2c2.S
+++ b/cpu/mpc824x/drivers/i2c/i2c2.S
@@ -16,20 +16,20 @@
  *
  * output: r3 - register content
  **********************************************************/
-      .text
-      .align 2
-      .global load_runtime_reg
+	.text
+	.align 2
+	.global load_runtime_reg
 load_runtime_reg:
 
-/*		  xor r5,r5,r5
-*         or  r5,r5,r3
-*
-*	      lwbrx	r3,r4,r5
-*/
-	      lwbrx r3,r4,r3
-	      sync
+/*	xor r5,r5,r5
+ *	or  r5,r5,r3
+ *
+ *	lwbrx	r3,r4,r5
+ */
+	lwbrx r3,r4,r3
+	sync
 
- 	      bclr 20, 0
+	bclr 20, 0
 
 /****************************************************************
  * function: store_runtime_reg
@@ -39,16 +39,14 @@ load_runtime_reg:
  *        r5 - new value to be stored
  *
  ****************************************************************/
-           .text
-           .align 2
-           .global store_runtime_reg
+	.text
+	.align 2
+	.global store_runtime_reg
 store_runtime_reg:
 
-	      stwbrx r5,  r4, r3
-	      sync
-
-              bclr   20,0
-
+	stwbrx r5,  r4, r3
+	sync
 
+	bclr   20,0
 
 #endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc824x/drivers/i2c/i2c_export.h b/cpu/mpc824x/drivers/i2c/i2c_export.h
index 17403ea..6264d18 100644
--- a/cpu/mpc824x/drivers/i2c/i2c_export.h
+++ b/cpu/mpc824x/drivers/i2c/i2c_export.h
@@ -71,11 +71,11 @@ typedef enum _i2c_restart
 extern I2C_Status I2C_Initialize(
 	unsigned char addr,            /* driver's I2C slave address */
 	I2C_INTERRUPT_MODE en_int,     /* 1 - enable I2C interrupt
-	                                * 0 - disable I2C interrupt
-	                                */
-        int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-                                                 * provided by application
-                                                 */
+					* 0 - disable I2C interrupt
+					*/
+	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+						 * provided by application
+						 */
 
 /* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
  * are implemented.  Both are only in polling mode.
@@ -92,12 +92,12 @@ extern I2C_Status I2C_Initialize(
  *        I2C_RESTART, this is a continuation of existing transaction
  */
 extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
-                                      I2C_TRANSACTION_MODE act,
-                                      unsigned char i2c_addr,
-                                      unsigned char data_addr,
-                                      int len,
-                                      char *buffer,
-                                      I2C_STOP_MODE stop,
-                                      int retry,
-                                      I2C_RESTART_MODE rsta);
+				      I2C_TRANSACTION_MODE act,
+				      unsigned char i2c_addr,
+				      unsigned char data_addr,
+				      int len,
+				      char *buffer,
+				      I2C_STOP_MODE stop,
+				      int retry,
+				      I2C_RESTART_MODE rsta);
 #endif
diff --git a/cpu/mpc824x/drivers/i2c_export.h b/cpu/mpc824x/drivers/i2c_export.h
index 17403ea..6264d18 100644
--- a/cpu/mpc824x/drivers/i2c_export.h
+++ b/cpu/mpc824x/drivers/i2c_export.h
@@ -71,11 +71,11 @@ typedef enum _i2c_restart
 extern I2C_Status I2C_Initialize(
 	unsigned char addr,            /* driver's I2C slave address */
 	I2C_INTERRUPT_MODE en_int,     /* 1 - enable I2C interrupt
-	                                * 0 - disable I2C interrupt
-	                                */
-        int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-                                                 * provided by application
-                                                 */
+					* 0 - disable I2C interrupt
+					*/
+	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+						 * provided by application
+						 */
 
 /* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
  * are implemented.  Both are only in polling mode.
@@ -92,12 +92,12 @@ extern I2C_Status I2C_Initialize(
  *        I2C_RESTART, this is a continuation of existing transaction
  */
 extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
-                                      I2C_TRANSACTION_MODE act,
-                                      unsigned char i2c_addr,
-                                      unsigned char data_addr,
-                                      int len,
-                                      char *buffer,
-                                      I2C_STOP_MODE stop,
-                                      int retry,
-                                      I2C_RESTART_MODE rsta);
+				      I2C_TRANSACTION_MODE act,
+				      unsigned char i2c_addr,
+				      unsigned char data_addr,
+				      int len,
+				      char *buffer,
+				      I2C_STOP_MODE stop,
+				      int retry,
+				      I2C_RESTART_MODE rsta);
 #endif
diff --git a/cpu/mpc824x/drivers/i2o.h b/cpu/mpc824x/drivers/i2o.h
index 87225ab..c47253d 100644
--- a/cpu/mpc824x/drivers/i2o.h
+++ b/cpu/mpc824x/drivers/i2o.h
@@ -123,11 +123,11 @@ typedef struct _i2o_im_stat
  PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
  **/
 extern I2OSTATUS I2OMsgEnable( LOCATION,            /*  REMOTE/LOCAL   */
-                               unsigned int base,   /* pcsrbar/eumbbar */
-                               unsigned char n );   /* b'1' - msg 0
-						                             * b'10'- msg 1
-						                             * b'11'- both
-						                             */
+			       unsigned int base,   /* pcsrbar/eumbbar */
+			       unsigned char n );   /* b'1' - msg 0
+									     * b'10'- msg 1
+									     * b'11'- both
+									     */
 
 /**
  Disable the interrupt associated with in/out bound msg
@@ -137,11 +137,11 @@ extern I2OSTATUS I2OMsgEnable( LOCATION,            /*  REMOTE/LOCAL   */
  PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
  **/
 extern I2OSTATUS I2OMsgDisable( LOCATION,          /*  REMOTE/LOCAL   */
-                                unsigned int base, /* pcsrbar/eumbbar */
-                                unsigned char n ); /* b'1' - msg 0
-			   			                            * b'10'- msg 1
-						                            * b'11'- both
-						                            */
+				unsigned int base, /* pcsrbar/eumbbar */
+				unsigned char n ); /* b'1' - msg 0
+									    * b'10'- msg 1
+									    * b'11'- both
+									    */
 
 /**
  Read the msg register either from local inbound msg 0/1,
@@ -154,9 +154,9 @@ extern I2OSTATUS I2OMsgDisable( LOCATION,          /*  REMOTE/LOCAL   */
  Otherwise local inbound msg is read.
  **/
 extern I2OSTATUS I2OMsgGet ( LOCATION,                 /* REMOTE/LOCAL */
-                             unsigned int base,        /*pcsrbar/eumbbar */
-                             unsigned int n,           /* 0 or 1 */
-                             unsigned int *msg );
+			     unsigned int base,        /*pcsrbar/eumbbar */
+			     unsigned int n,           /* 0 or 1 */
+			     unsigned int *msg );
 
 /**
  Write to nth Msg register either on local outbound msg 0/1,
@@ -169,9 +169,9 @@ extern I2OSTATUS I2OMsgGet ( LOCATION,                 /* REMOTE/LOCAL */
  Otherwise local outbound msg is written.
  **/
 extern I2OSTATUS I2OMsgPost( LOCATION,                 /* REMOTE/LOCAL */
-                                unsigned int base,        /*pcsrbar/eumbbar */
-                                unsigned int n,           /* 0 or 1 */
-                                unsigned int msg );
+				unsigned int base,        /*pcsrbar/eumbbar */
+				unsigned int n,           /* 0 or 1 */
+				unsigned int msg );
 
 /**
  Enable the In/Out DoorBell Interrupt
@@ -183,8 +183,8 @@ extern I2OSTATUS I2OMsgPost( LOCATION,                 /* REMOTE/LOCAL */
  PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
  **/
 extern I2OSTATUS I2ODBEnable( LOCATION,            /*  REMOTE/LOCAL   */
-                              unsigned int base,   /* pcsrbar/eumbbar */
-                              unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+			      unsigned int base,   /* pcsrbar/eumbbar */
+			      unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
 
 /**
  Disable the In/Out DoorBell Interrupt
@@ -195,8 +195,8 @@ extern I2OSTATUS I2ODBEnable( LOCATION,            /*  REMOTE/LOCAL   */
 
  **/
 extern I2OSTATUS I2ODBDisable( LOCATION,              /*  REMOTE/LOCAL   */
-                               unsigned int base,     /* pcsrbar/eumbbar */
-                               unsigned int in_db );  /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+			       unsigned int base,     /* pcsrbar/eumbbar */
+			       unsigned int in_db );  /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
 
 /**
  Read a local indoorbell register, or an outdoorbell of devices.
@@ -209,7 +209,7 @@ extern I2OSTATUS I2ODBDisable( LOCATION,              /*  REMOTE/LOCAL   */
  Otherwise local in doorbell is read
  **/
 extern unsigned int I2ODBGet( LOCATION,             /*  REMOTE/LOCAL   */
-                              unsigned int base);   /* pcsrbar/eumbbar */
+			      unsigned int base);   /* pcsrbar/eumbbar */
 
 /**
  Write to a local outdoorbell register, or an indoorbell register of devices.
@@ -221,8 +221,8 @@ extern unsigned int I2ODBGet( LOCATION,             /*  REMOTE/LOCAL   */
  Otherwise local out doorbell is written
  **/
 extern void I2ODBPost( LOCATION,                 /*  REMOTE/LOCAL   */
-                       unsigned int base,        /* pcsrbar/eumbbar */
-                       unsigned int msg );       /*   in   / out    */
+		       unsigned int base,        /* pcsrbar/eumbbar */
+		       unsigned int msg );       /*   in   / out    */
 
 /**
  Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
@@ -251,8 +251,8 @@ extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
  MUCR.
  **/
 extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
-				              QUEUE_SIZE,
-				              unsigned int qba);/* queue base address that must be aligned at 1M */
+					      QUEUE_SIZE,
+					      unsigned int qba);/* queue base address that must be aligned at 1M */
 /**
  Enable the circular queue
  **/
@@ -296,8 +296,8 @@ extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
  Unless both free queues are initialized, allocating a free MF will return 0xffffffff
  **/
 extern I2OSTATUS I2OFIFOAlloc( LOCATION,
-			 	               unsigned int base,
-				               void         **pMsg);
+					       unsigned int base,
+					       void         **pMsg);
 /**
  Free a used msg frame back to free queue
  PCI Master frees a MFA through outbound queue port of device(OFQPR)
@@ -310,8 +310,8 @@ extern I2OSTATUS I2OFIFOAlloc( LOCATION,
  and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
  **/
 extern I2OSTATUS I2OFIFOFree( LOCATION,
-			                  unsigned int base,
-			                  void        *pMsg );
+					  unsigned int base,
+					  void        *pMsg );
 
 /**
  Post a msg into FIFO
@@ -322,8 +322,8 @@ extern I2OSTATUS I2OFIFOFree( LOCATION,
  Otherwise queue overflow interrupt will assert.
  **/
 extern I2OSTATUS I2OFIFOPost( LOCATION,
-		                      unsigned int base,
-		                      void         *pMsg );
+				      unsigned int base,
+				      void         *pMsg );
 
 /**
  Read a msg from FIFO
@@ -331,14 +331,14 @@ extern I2OSTATUS I2OFIFOPost( LOCATION,
  while local processor reads a msg from its inbound post queue(IPTPR)
  **/
 extern I2OSTATUS I2OFIFOGet( LOCATION,
-	 		                  unsigned int base,
+					  unsigned int base,
 							  void     **pMsg );
 
 /**
  Get the I2O PCI configuration identification register
  **/
 extern I2OSTATUS I2OPCIConfigGet( LOCATION,
-			                   unsigned int base,
+					   unsigned int base,
 							   I2OIOP *);
 
 #endif
diff --git a/cpu/mpc824x/drivers/i2o/i2o.h b/cpu/mpc824x/drivers/i2o/i2o.h
index 26f7c5c..71572b2 100644
--- a/cpu/mpc824x/drivers/i2o/i2o.h
+++ b/cpu/mpc824x/drivers/i2o/i2o.h
@@ -124,11 +124,11 @@ typedef struct _i2o_im_stat
  PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
  **/
 extern I2OSTATUS I2OMsgEnable( LOCATION,            /*  REMOTE/LOCAL   */
-                               unsigned int base,   /* pcsrbar/eumbbar */
-                               unsigned char n );   /* b'1' - msg 0
-						                             * b'10'- msg 1
-						                             * b'11'- both
-						                             */
+			       unsigned int base,   /* pcsrbar/eumbbar */
+			       unsigned char n );   /* b'1' - msg 0
+									     * b'10'- msg 1
+									     * b'11'- both
+									     */
 
 /**
  Disable the interrupt associated with in/out bound msg
@@ -138,11 +138,11 @@ extern I2OSTATUS I2OMsgEnable( LOCATION,            /*  REMOTE/LOCAL   */
  PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
  **/
 extern I2OSTATUS I2OMsgDisable( LOCATION,          /*  REMOTE/LOCAL   */
-                                unsigned int base, /* pcsrbar/eumbbar */
-                                unsigned char n ); /* b'1' - msg 0
-			   			                            * b'10'- msg 1
-						                            * b'11'- both
-						                            */
+				unsigned int base, /* pcsrbar/eumbbar */
+				unsigned char n ); /* b'1' - msg 0
+									    * b'10'- msg 1
+									    * b'11'- both
+									    */
 
 /**
  Read the msg register either from local inbound msg 0/1,
@@ -155,9 +155,9 @@ extern I2OSTATUS I2OMsgDisable( LOCATION,          /*  REMOTE/LOCAL   */
  Otherwise local inbound msg is read.
  **/
 extern I2OSTATUS I2OMsgGet ( LOCATION,                 /* REMOTE/LOCAL */
-                             unsigned int base,        /*pcsrbar/eumbbar */
-                             unsigned int n,           /* 0 or 1 */
-                             unsigned int *msg );
+			     unsigned int base,        /*pcsrbar/eumbbar */
+			     unsigned int n,           /* 0 or 1 */
+			     unsigned int *msg );
 
 /**
  Write to nth Msg register either on local outbound msg 0/1,
@@ -170,9 +170,9 @@ extern I2OSTATUS I2OMsgGet ( LOCATION,                 /* REMOTE/LOCAL */
  Otherwise local outbound msg is written.
  **/
 extern I2OSTATUS I2OMsgPost( LOCATION,                 /* REMOTE/LOCAL */
-                                unsigned int base,        /*pcsrbar/eumbbar */
-                                unsigned int n,           /* 0 or 1 */
-                                unsigned int msg );
+				unsigned int base,        /*pcsrbar/eumbbar */
+				unsigned int n,           /* 0 or 1 */
+				unsigned int msg );
 
 /**
  Enable the In/Out DoorBell Interrupt
@@ -184,8 +184,8 @@ extern I2OSTATUS I2OMsgPost( LOCATION,                 /* REMOTE/LOCAL */
  PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
  **/
 extern I2OSTATUS I2ODBEnable( LOCATION,            /*  REMOTE/LOCAL   */
-                              unsigned int base,   /* pcsrbar/eumbbar */
-                              unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+			      unsigned int base,   /* pcsrbar/eumbbar */
+			      unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
 
 /**
  Disable the In/Out DoorBell Interrupt
@@ -196,8 +196,8 @@ extern I2OSTATUS I2ODBEnable( LOCATION,            /*  REMOTE/LOCAL   */
 
  **/
 extern I2OSTATUS I2ODBDisable( LOCATION,              /*  REMOTE/LOCAL   */
-                               unsigned int base,     /* pcsrbar/eumbbar */
-                               unsigned int in_db );  /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+			       unsigned int base,     /* pcsrbar/eumbbar */
+			       unsigned int in_db );  /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
 
 /**
  Read a local indoorbell register, or an outdoorbell of devices.
@@ -210,7 +210,7 @@ extern I2OSTATUS I2ODBDisable( LOCATION,              /*  REMOTE/LOCAL   */
  Otherwise local in doorbell is read
  **/
 extern unsigned int I2ODBGet( LOCATION,             /*  REMOTE/LOCAL   */
-                              unsigned int base);   /* pcsrbar/eumbbar */
+			      unsigned int base);   /* pcsrbar/eumbbar */
 
 /**
  Write to a local outdoorbell register, or an indoorbell register of devices.
@@ -222,8 +222,8 @@ extern unsigned int I2ODBGet( LOCATION,             /*  REMOTE/LOCAL   */
  Otherwise local out doorbell is written
  **/
 extern void I2ODBPost( LOCATION,                 /*  REMOTE/LOCAL   */
-                       unsigned int base,        /* pcsrbar/eumbbar */
-                       unsigned int msg );       /*   in   / out    */
+		       unsigned int base,        /* pcsrbar/eumbbar */
+		       unsigned int msg );       /*   in   / out    */
 
 /**
  Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
@@ -252,8 +252,8 @@ extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
  MUCR.
  **/
 extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
-				              QUEUE_SIZE,
-				              unsigned int qba);/* queue base address that must be aligned at 1M */
+					      QUEUE_SIZE,
+					      unsigned int qba);/* queue base address that must be aligned at 1M */
 /**
  Enable the circular queue
  **/
@@ -297,8 +297,8 @@ extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
  Unless both free queues are initialized, allocating a free MF will return 0xffffffff
  **/
 extern I2OSTATUS I2OFIFOAlloc( LOCATION,
-			 	               unsigned int base,
-				               void         **pMsg);
+					       unsigned int base,
+					       void         **pMsg);
 /**
  Free a used msg frame back to free queue
  PCI Master frees a MFA through outbound queue port of device(OFQPR)
@@ -311,8 +311,8 @@ extern I2OSTATUS I2OFIFOAlloc( LOCATION,
  and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
  **/
 extern I2OSTATUS I2OFIFOFree( LOCATION,
-			                  unsigned int base,
-			                  void        *pMsg );
+					  unsigned int base,
+					  void        *pMsg );
 
 /**
  Post a msg into FIFO
@@ -323,8 +323,8 @@ extern I2OSTATUS I2OFIFOFree( LOCATION,
  Otherwise queue overflow interrupt will assert.
  **/
 extern I2OSTATUS I2OFIFOPost( LOCATION,
-		                      unsigned int base,
-		                      void         *pMsg );
+				      unsigned int base,
+				      void         *pMsg );
 
 /**
  Read a msg from FIFO
@@ -332,14 +332,14 @@ extern I2OSTATUS I2OFIFOPost( LOCATION,
  while local processor reads a msg from its inbound post queue(IPTPR)
  **/
 extern I2OSTATUS I2OFIFOGet( LOCATION,
-	 		                  unsigned int base,
+					  unsigned int base,
 							  void     **pMsg );
 
 /**
  Get the I2O PCI configuration identification register
  **/
 extern I2OSTATUS I2OPCIConfigGet( LOCATION,
-			                   unsigned int base,
+					   unsigned int base,
 							   I2OIOP *);
 
 #endif
diff --git a/cpu/mpc824x/drivers/i2o/i2o1.c b/cpu/mpc824x/drivers/i2o/i2o1.c
index d840af0..f058151 100644
--- a/cpu/mpc824x/drivers/i2o/i2o1.c
+++ b/cpu/mpc824x/drivers/i2o/i2o1.c
@@ -34,10 +34,10 @@ FIFOSTAT fifo_stat = { QSIZE_4K, 0xffffffff };
  * PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE)
  ************************************************************************************/
 I2OSTATUS I2OMsgEnable ( LOCATION loc,        /*  REMOTE/LOCAL   */
-                         unsigned int base,   /* pcsrbar/eumbbar */
-                         unsigned char n )    /* b'1' - msg 0
-				               * b'10'- msg 1
-		 		               * b'11'- both
+			 unsigned int base,   /* pcsrbar/eumbbar */
+			 unsigned char n )    /* b'1' - msg 0
+					       * b'10'- msg 1
+					       * b'11'- both
 					       */
 {
     unsigned int reg, val;
@@ -73,8 +73,8 @@ I2OSTATUS I2OMsgEnable ( LOCATION loc,        /*  REMOTE/LOCAL   */
  *  PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE)
  *********************************************************************************/
 I2OSTATUS I2OMsgDisable( LOCATION loc,      /*  REMOTE/LOCAL   */
-                         unsigned int base, /* pcsrbar/eumbbar */
-                         unsigned char n )  /* b'1' - msg 0
+			 unsigned int base, /* pcsrbar/eumbbar */
+			 unsigned char n )  /* b'1' - msg 0
 					     * b'10'- msg 1
 					     * b'11'- both
 					     */
@@ -114,9 +114,9 @@ I2OSTATUS I2OMsgDisable( LOCATION loc,      /*  REMOTE/LOCAL   */
  * If it is remote, outbound msg on the device is read; otherwise local inbound msg is read
  *************************************************************************/
 I2OSTATUS I2OMsgGet ( LOCATION loc,             /* REMOTE/LOCAL */
-                         unsigned int base,        /*pcsrbar/eumbbar */
-                         unsigned int n,           /* 0 or 1 */
-                         unsigned int *msg )
+			 unsigned int base,        /*pcsrbar/eumbbar */
+			 unsigned int n,           /* 0 or 1 */
+			 unsigned int *msg )
 {
     if ( n >= I2O_NUM_MSG || msg == 0 )
     {
@@ -151,9 +151,9 @@ I2OSTATUS I2OMsgGet ( LOCATION loc,             /* REMOTE/LOCAL */
  * If it is remote, inbound msg on the device is written; otherwise local outbound msg is written
  ***************************************************************/
 I2OSTATUS I2OMsgPost( LOCATION loc,             /* REMOTE/LOCAL */
-                      unsigned int base,        /*pcsrbar/eumbbar */
-                      unsigned int n,           /* 0 or 1 */
-                      unsigned int msg )
+		      unsigned int base,        /*pcsrbar/eumbbar */
+		      unsigned int n,           /* 0 or 1 */
+		      unsigned int msg )
 {
     if ( n >= I2O_NUM_MSG )
     {
@@ -190,8 +190,8 @@ I2OSTATUS I2OMsgPost( LOCATION loc,             /* REMOTE/LOCAL */
  * PCI master needs to enable the outbound doorbell interrupts of device it wants to handle
  **********************************************************************/
 I2OSTATUS I2ODBEnable( LOCATION loc,        /*  REMOTE/LOCAL   */
-                  unsigned int base,   /* pcsrbar/eumbbar */
-                  unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+		  unsigned int base,   /* pcsrbar/eumbbar */
+		  unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
 {
 
     /* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device
@@ -209,15 +209,15 @@ I2OSTATUS I2ODBEnable( LOCATION loc,        /*  REMOTE/LOCAL   */
 	/* pcsrbar is base */
 	val = load_runtime_reg( base, I2O_OMIMR );
 	val &= 0xfffffff7;
-        store_runtime_reg( base, I2O_OMIMR , val );
+	store_runtime_reg( base, I2O_OMIMR , val );
     }
     else
     {
 	/* eumbbar is base */
 	val = load_runtime_reg( base, I2O_IMIMR);
-        in_db = ( (~in_db) & 0x3 ) << 3;
-        val = ( val & 0xffffffe7) | in_db;
-        store_runtime_reg( base,  I2O_IMIMR, val );
+	in_db = ( (~in_db) & 0x3 ) << 3;
+	val = ( val & 0xffffffe7) | in_db;
+	store_runtime_reg( base,  I2O_IMIMR, val );
     }
 
     return I2OSUCCESS;
@@ -237,8 +237,8 @@ I2OSTATUS I2ODBEnable( LOCATION loc,        /*  REMOTE/LOCAL   */
  * PCI master needs to disable outbound doorbell interrupts of device it is not interested
  ************************************************************************************/
 I2OSTATUS I2ODBDisable( LOCATION loc,          /*  REMOTE/LOCAL   */
-                        unsigned int base,     /* pcsrbar/eumbbar */
-                        unsigned int in_db )   /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+			unsigned int base,     /* pcsrbar/eumbbar */
+			unsigned int in_db )   /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
 {
     /* LOCATION - REMOTE : handle device's out bound message initialization
      *            LOCAL  : handle local in bound message initialization
@@ -255,14 +255,14 @@ I2OSTATUS I2ODBDisable( LOCATION loc,          /*  REMOTE/LOCAL   */
 	/* pcsrbar is the base */
 	val = load_runtime_reg( base, I2O_OMIMR );
 	val |= 0x8;
-        store_runtime_reg( base, I2O_OMIMR, val );
+	store_runtime_reg( base, I2O_OMIMR, val );
     }
     else
     {
 	    val = load_runtime_reg( base, I2O_IMIMR);
-            in_db = ( in_db & 0x3 ) << 3;
-            val |= in_db;
-            store_runtime_reg( base, I2O_IMIMR, val );
+	    in_db = ( in_db & 0x3 ) << 3;
+	    val |= in_db;
+	    store_runtime_reg( base, I2O_IMIMR, val );
     }
 
     return I2OSUCCESS;
@@ -287,22 +287,22 @@ I2OSTATUS I2ODBDisable( LOCATION loc,          /*  REMOTE/LOCAL   */
  * will cause interrupt pending.
  *********************************************************************************/
 unsigned int I2ODBGet( LOCATION loc,         /*  REMOTE/LOCAL   */
-                       unsigned int base)    /* pcsrbar/eumbbar */
+		       unsigned int base)    /* pcsrbar/eumbbar */
 {
     unsigned int msg, val;
 
     if ( loc == REMOTE )
     {
 	/* read outbound doorbell register of device, pcsrbar is the base */
-        val = load_runtime_reg( base, I2O_ODBR );
-        msg = val & 0xe0000000;
-        store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */
+	val = load_runtime_reg( base, I2O_ODBR );
+	msg = val & 0xe0000000;
+	store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */
     }
     else
     {
 	/* read the inbound doorbell register, eumbbar is the base */
-        val = load_runtime_reg( base, I2O_IDBR );
-        store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */
+	val = load_runtime_reg( base, I2O_IDBR );
+	store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */
 	msg = val;
     }
 
@@ -323,8 +323,8 @@ unsigned int I2ODBGet( LOCATION loc,         /*  REMOTE/LOCAL   */
  * Otherwise local out doorbell is written
  *********************************************************************/
 void I2ODBPost( LOCATION loc,             /*  REMOTE/LOCAL   */
-                unsigned int base,        /* pcsrbar/eumbbar */
-                unsigned int msg )        /*   in   / out    */
+		unsigned int base,        /* pcsrbar/eumbbar */
+		unsigned int msg )        /*   in   / out    */
 {
     if ( loc == REMOTE )
     {
@@ -527,8 +527,8 @@ void I2OFIFODisable( unsigned int eumbbar )
  *
  ****************************************************/
 I2OSTATUS I2OFIFOAlloc( LOCATION loc,
-		        unsigned int base,
-		        void         **pMsg )
+			unsigned int base,
+			void         **pMsg )
 {
     I2OSTATUS stat = I2OSUCCESS;
     void *pHdr, *pTil;
@@ -543,12 +543,12 @@ I2OSTATUS I2OFIFOAlloc( LOCATION loc,
     {
 	/* pcsrbar is the base and read the inbound free tail ptr */
 	pTil = (void *)load_runtime_reg( base, I2O_IFQPR );
-        if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
-        {
+	if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
+	{
 	    stat = I2OQUEEMPTY;
-        }
+	}
 	else
-        {
+	{
 	    *pMsg = pTil;
 	}
     }
@@ -562,7 +562,7 @@ I2OSTATUS I2OFIFOAlloc( LOCATION loc,
 	if ( pHdr == pTil )
 	{
 	    /* hdr and til point to the same fifo item, no free MFA */
-            stat = I2OQUEEMPTY;
+	    stat = I2OQUEEMPTY;
 	}
 	else
 	{
@@ -615,7 +615,7 @@ I2OSTATUS I2OFIFOFree( LOCATION loc,
     {
 	/* eumbbar is the base */
 	pHdr = (void **)load_runtime_reg( base, I2O_IFHPR );
-        pTil = (void **)load_runtime_reg( base, I2O_IFTPR );
+	pTil = (void **)load_runtime_reg( base, I2O_IFTPR );
 
 	/* store MFA */
 	*pHdr = pMsg;
@@ -633,7 +633,7 @@ I2OSTATUS I2OFIFOFree( LOCATION loc,
 	if ( pHdr != pTil )
 	{
 	   store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
-        }
+	}
 	else
 	{
 	    stat = I2OQUEFULL;
@@ -677,7 +677,7 @@ I2OSTATUS I2OFIFOPost( LOCATION loc,
     {
 	/* eumbbar is the base */
 	pHdr = (void **)load_runtime_reg( base, I2O_OPHPR );
-        pTil = (void **)load_runtime_reg( base, I2O_OPTPR );
+	pTil = (void **)load_runtime_reg( base, I2O_OPTPR );
 
 	/* store MFA */
 	*pHdr = pMsg;
@@ -695,7 +695,7 @@ I2OSTATUS I2OFIFOPost( LOCATION loc,
 	if ( pHdr != pTil )
 	{
 	   store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
-        }
+	}
 	else
 	{
 	    stat = I2OQUEFULL;
@@ -734,12 +734,12 @@ I2OSTATUS I2OFIFOGet( LOCATION loc,
     {
 	/* pcsrbar is the base */
 	pTil = (void *)load_runtime_reg( base, I2O_OFQPR );
-        if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
-        {
+	if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
+	{
 	    stat = I2OQUEEMPTY;
-        }
+	}
 	else
-        {
+	{
 	    *pMsg = pTil;
 	}
     }
@@ -753,7 +753,7 @@ I2OSTATUS I2OFIFOGet( LOCATION loc,
 	if ( pHdr == pTil )
 	{
 	    /* no free MFA */
-            stat = I2OQUEEMPTY;
+	    stat = I2OQUEEMPTY;
 	}
 	else
 	{
@@ -783,8 +783,8 @@ I2OSTATUS I2OFIFOGet( LOCATION loc,
  *       should pass eumbbar.
  *********************************************************/
 I2OSTATUS I2OPCIConfigGet( LOCATION loc,
-		        unsigned int base,
-		        I2OIOP * val)
+			unsigned int base,
+			I2OIOP * val)
 {
     unsigned int tmp;
     if ( val == 0 )
diff --git a/cpu/mpc824x/drivers/i2o/i2o2.S b/cpu/mpc824x/drivers/i2o/i2o2.S
index 1033979..990f9ef 100644
--- a/cpu/mpc824x/drivers/i2o/i2o2.S
+++ b/cpu/mpc824x/drivers/i2o/i2o2.S
@@ -19,12 +19,12 @@
 load_runtime_reg:
 
 		  xor r5,r5,r5
-          or  r5,r5,r3       /* save eumbbar */
+	  or  r5,r5,r3       /* save eumbbar */
 
 	      lwbrx	r3,r4,r5
 	      sync
 
- 	      bclr 20, 0
+	      bclr 20, 0
 
 /****************************************************************
  * function: store_runtime_reg
@@ -34,9 +34,9 @@ load_runtime_reg:
  *        r5 - new value to be stored
  *
  ****************************************************************/
-           .text
-           .align 2
-           .global store_runtime_reg
+	   .text
+	   .align 2
+	   .global store_runtime_reg
 store_runtime_reg:
 
 		  xor r0,r0,r0
@@ -45,4 +45,3 @@ store_runtime_reg:
 	      sync
 
 		  bclr   20,0
-