ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

5 files changed, 0 insertions, 1035 deletions

diff --git a/cpu/mpc824x/drivers/epic/README b/cpu/mpc824x/drivers/epic/README
deleted file mode 100644
index 5798996..0000000
--- a/cpu/mpc824x/drivers/epic/README
+++ /dev/null
@@ -1,102 +0,0 @@
-CONTENT:
-
-   epic.h
-   epic1.c
-   epic2.s
-
-WHAT ARE THESE FILES:
-
-These files contain MPC8240 (Kahlua) EPIC
-driver routines. The driver routines are not
-written for any specific operating system.
-They serves the purpose of code sample, and
-jump-start for using the MPC8240 EPIC unit.
-
-For the reason of correctness of C language
-syntax, these files are compiled by Metaware
-C compiler and assembler.
-
-ENDIAN NOTATION:
-
-The algorithm is designed for big-endian mode,
-software is responsible for byte swapping.
-
-USAGE:
-
-1. The host system that is running on MPC8240
-   shall link the files listed here. The memory
-   location of driver routines shall take into
-   account of that driver routines need to run
-   in supervisor mode and they process external
-   interrupts.
-
-   The routine epic_exception shall be called by
-   exception vector at location 0x500, i.e.,
-   603e core external exception vector.
-
-2. The host system is responsible for configuring
-   the MPC8240 including Embedded Utilities Memory
-   Block. All EPIC driver functions require the
-   content of Embedded Utilities Memory Block
-   Base Address Register, EUMBBAR, as the first
-   parameter.
-
-3. Before EPIC unit of MPC8240 can be used,
-   initialize EPIC unit by calling epicInit
-   with the corresponding parameters.
-
-   The initialization shall disable the 603e
-   core External Exception by calling CoreExtIntDisable( ).
-   Next, call epicInit( ). Last, enable the 603e core
-   External Exception by calling CoreExtIntEnable( ).
-
-4. After EPIC unit has been successfully initialized,
-   epicIntSourceSet( ) shall be used to register each
-   external interrupt source. Anytime, an external
-   interrupt source can be disabled or enabled by
-   calling corresponding function, epicIntDisable( ),
-   or epicIntEnable( ).
-
-   Global Timers' resource, base count and frequency,
-   can be changed by calling epicTmFrequencySet( )
-   and epicTmBaseSet( ).
-
-   To stop counting a specific global timer, use
-   the function, epicTmInhibit while epicTmEnable
-   can be used to start counting a timer.
-
-5. To mask a set of external interrupts that are
-   are certain level below, epicIntPrioritySet( )
-   can be used. For example, if the processor's
-   current task priority register is set to 0x7,
-   only interrupts of priority 0x8 or higher will
-   be passed to the processor.
-
-   Be careful when using this function. It may
-   corrupt the current interrupt pending, selector,
-   and request registers, resulting an invalid vetor.
-
-   After enabling an interrupt, disable it may also
-   cause an invalid vector. User may consider using
-   the spurious vector interrupt service routine to
-   handle this case.
-
-6. The EPIC driver routines contains a set
-   of utilities, Set and Get, for host system
-   to query and modify the desired EPIC source
-   registers.
-
-7. Each external interrupt source shall register
-   its interrupt service routine. The routine
-   shall contain all interrupt source specific
-   processes and keep as short as possible.
-
-   Special customized end of interrupt routine
-   is optional. If it is needed, it shall contain
-   the external interrupt source specific end of
-   interrupt process.
-
-   External interrupt exception vector at 0x500
-   shall always call the epicEOI just before
-   rfi instruction. Refer to the routine,
-   epic_exception, for a code sample.
diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h
deleted file mode 100644
index 58f81c5..0000000
--- a/cpu/mpc824x/drivers/epic/epic.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*********************************************************************
- * mpc8240epic.h - EPIC module of the MPC8240 micro-controller
- *
- * Copyrigh 1999  Motorola Inc.
- *
- * Modification History:
- * =====================
- * 01a,04Feb99,My  Created.
- * 15Nov200, robt -modified to use in U-Boot
- *
-*/
-
-#ifndef __INCEPICh
-#define __INCEPICh
-
-#define ULONG unsigned long
-#define MAXVEC             20
-#define MAXIRQ        5 /* IRQs */
-#define EPIC_DIRECT_IRQ     0 /* Direct interrupt type */
-
-/* EPIC register addresses */
-
-#define EPIC_EUMBBAR      0x40000     /* EUMBBAR of EPIC  */
-#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */
-#define EPIC_GLOBAL_REG   (EPIC_EUMBBAR + 0x01020)/* Global config.  */
-#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */
-#define EPIC_VENDOR_ID_REG  (EPIC_EUMBBAR + 0x01080)/* Vendor id */
-#define EPIC_PROC_INIT_REG  (EPIC_EUMBBAR + 0x01090)/* Processor init. */
-#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */
-#define EPIC_TM_FREQ_REG  (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */
-
-#define EPIC_TM0_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/
-#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/
-#define EPIC_TM0_VEC_REG  (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/
-#define EPIC_TM0_DES_REG  (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */
-
-#define EPIC_TM1_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/
-#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/
-#define EPIC_TM1_VEC_REG  (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/
-#define EPIC_TM1_DES_REG  (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */
-
-#define EPIC_TM2_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/
-#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/
-#define EPIC_TM2_VEC_REG  (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/
-#define EPIC_TM2_DES_REG  (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */
-
-#define EPIC_TM3_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/
-#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/
-#define EPIC_TM3_VEC_REG  (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/
-#define EPIC_TM3_DES_REG  (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */
-
-#define EPIC_EX_INT0_VEC_REG  (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */
-#define EPIC_EX_INT0_DES_REG  (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/
-#define EPIC_EX_INT1_VEC_REG  (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */
-#define EPIC_EX_INT1_DES_REG  (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/
-#define EPIC_EX_INT2_VEC_REG  (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */
-#define EPIC_EX_INT2_DES_REG  (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/
-#define EPIC_EX_INT3_VEC_REG  (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */
-#define EPIC_EX_INT3_DES_REG  (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/
-#define EPIC_EX_INT4_VEC_REG  (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */
-#define EPIC_EX_INT4_DES_REG  (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/
-
-#define EPIC_SR_INT0_VEC_REG  (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */
-#define EPIC_SR_INT0_DES_REG  (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */
-#define EPIC_SR_INT1_VEC_REG  (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */
-#define EPIC_SR_INT1_DES_REG  (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/
-#define EPIC_SR_INT2_VEC_REG  (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */
-#define EPIC_SR_INT2_DES_REG  (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/
-#define EPIC_SR_INT3_VEC_REG  (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */
-#define EPIC_SR_INT3_DES_REG  (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/
-#define EPIC_SR_INT4_VEC_REG  (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */
-#define EPIC_SR_INT4_DES_REG  (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/
-
-#define EPIC_SR_INT5_VEC_REG  (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */
-#define EPIC_SR_INT5_DES_REG  (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/
-#define EPIC_SR_INT6_VEC_REG  (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */
-#define EPIC_SR_INT6_DES_REG  (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/
-#define EPIC_SR_INT7_VEC_REG  (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */
-#define EPIC_SR_INT7_DES_REG  (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/
-#define EPIC_SR_INT8_VEC_REG  (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */
-#define EPIC_SR_INT8_DES_REG  (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/
-#define EPIC_SR_INT9_VEC_REG  (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */
-#define EPIC_SR_INT9_DES_REG  (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/
-
-#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */
-#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/
-#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */
-#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/
-#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */
-#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/
-#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */
-#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/
-#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */
-#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/
-#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */
-#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/
-
-#define EPIC_I2C_INT_VEC_REG  (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/
-#define EPIC_I2C_INT_DES_REG  (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */
-#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/
-#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */
-#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/
-#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */
-#define EPIC_MSG_INT_VEC_REG  (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/
-#define EPIC_MSG_INT_DES_REG  (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest  */
-
-#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/
-#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
-#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
-
-#define EPIC_VEC_PRI_MASK      0x80000000 /* Mask Interrupt bit in IVPR */
-#define EPIC_VEC_PRI_DFLT_PRI  8          /* Interrupt Priority in IVPR */
-
-/* Error code */
-
-#define OK       0
-#define ERROR    -1
-
-/* function prototypes */
-
-void epicVendorId( unsigned int *step,
-       unsigned int *devId,
-       unsigned int *venId
-     );
-void epicFeatures( unsigned int *noIRQs,
-	     unsigned int *noCPUs,
-       unsigned int *VerId );
-extern void epicInit( unsigned int IRQType, unsigned int clkRatio);
-ULONG sysEUMBBARRead ( ULONG regNum );
-void sysEUMBBARWrite ( ULONG regNum, ULONG regVal);
-extern void epicTmFrequencySet( unsigned int frq );
-extern unsigned int epicTmFrequencyGet(void);
-extern unsigned int epicTmBaseSet( ULONG srcAddr,
-		 unsigned int cnt,
-		 unsigned int inhibit );
-extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val );
-extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val );
-extern unsigned int epicTmInhibit( unsigned int timer );
-extern unsigned int epicTmEnable( ULONG srcAdr );
-extern void CoreExtIntEnable(void);  /* Enable 603e external interrupts */
-extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */
-extern unsigned char epicIntTaskGet(void);
-extern void epicIntTaskSet( unsigned char val );
-extern unsigned int epicIntAck(void);
-extern void epicSprSet( unsigned int eumbbar, unsigned char );
-extern void epicConfigGet( unsigned int *clkRatio,
-	       unsigned int *serEnable );
-extern void SrcVecTableInit(void);
-extern unsigned int  epicModeGet(void);
-extern void epicIntEnable(int Vect);
-extern void epicIntDisable(int Vect);
-extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio);
-extern unsigned int epicIntAck(void);
-extern void epicEOI(void);
-extern int epicCurTaskPrioSet(int Vect);
-
-struct SrcVecTable
-    {
-     ULONG srcAddr;
-     char  srcName[40];
-    };
-
-#endif   /*  EPIC_H */
diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c
deleted file mode 100644
index ecbb42d..0000000
--- a/cpu/mpc824x/drivers/epic/epic1.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/**************************************************
- *
- * copyright @ motorola, 1999
- *
- *************************************************/
-#include <mpc824x.h>
-#include <common.h>
-#include "epic.h"
-
-
-#define PRINT(format, args...) printf(format , ## args)
-
-typedef void (*VOIDFUNCPTR)  (void);  /* ptr to function returning void */
-struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */
-    {
-    { EPIC_EX_INT0_VEC_REG,  "External Direct/Serial Source 0"},
-    { EPIC_EX_INT1_VEC_REG,  "External Direct/Serial Source 1"},
-    { EPIC_EX_INT2_VEC_REG,  "External Direct/Serial Source 2"},
-    { EPIC_EX_INT3_VEC_REG,  "External Direct/Serial Source 3"},
-    { EPIC_EX_INT4_VEC_REG,  "External Direct/Serial Source 4"},
-
-    { EPIC_SR_INT5_VEC_REG,  "External Serial Source 5"},
-    { EPIC_SR_INT6_VEC_REG,  "External Serial Source 6"},
-    { EPIC_SR_INT7_VEC_REG,  "External Serial Source 7"},
-    { EPIC_SR_INT8_VEC_REG,  "External Serial Source 8"},
-    { EPIC_SR_INT9_VEC_REG,  "External Serial Source 9"},
-    { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"},
-    { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"},
-    { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"},
-    { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"},
-    { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"},
-    { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"},
-
-    { EPIC_I2C_INT_VEC_REG,  "Internal I2C Source"},
-    { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"},
-    { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"},
-    { EPIC_MSG_INT_VEC_REG,  "Internal Message Source"},
-    };
-
-VOIDFUNCPTR intVecTbl[MAXVEC];    /* Interrupt vector table */
-
-
-/****************************************************************************
-*  epicInit - Initialize the EPIC registers
-*
-*  This routine resets the Global Configuration Register, thus it:
-*     -  Disables all interrupts
-*     -  Sets epic registers to reset values
-*     -  Sets the value of the Processor Current Task Priority to the
-*        highest priority (0xF).
-*  epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass
-*  Through or 8259 compatible mode).
-*
-*  If IRQType (input) is Direct IRQs:
-*     - IRQType is written to the SIE bit of the EPIC Interrupt
-*       Configuration register (ICR).
-*     - clkRatio is ignored.
-*  If IRQType is Serial IRQs:
-*     - both IRQType and clkRatio will be written to the ICR register
-*/
-
-void epicInit
-    (
-    unsigned int IRQType,      /* Direct or Serial */
-    unsigned int clkRatio      /* Clk Ratio for Serial IRQs */
-    )
-    {
-    ULONG tmp;
-
-    tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
-    tmp |= 0xa0000000;                  /* Set the Global Conf. register */
-    sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
-	/*
-	 * Wait for EPIC to reset - CLH
-	 */
-    while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
-    sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
-    tmp = sysEUMBBARRead(EPIC_INT_CONF_REG);    /* Read interrupt conf. reg */
-
-    if (IRQType == EPIC_DIRECT_IRQ)             /* direct mode */
-	sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
-    else                                        /* Serial mode */
-	{
-	tmp = (clkRatio << 28) | 0x08000000;    /* Set clock ratio */
-	sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
-	}
-
-    while (epicIntAck() != 0xff)       /* Clear all pending interrupts */
-		epicEOI();
-}
-
-/****************************************************************************
- *  epicIntEnable - Enable an interrupt source
- *
- *  This routine clears the mask bit of an external, an internal or
- *  a Timer register to enable the interrupt.
- *
- *  RETURNS:  None
- */
-void epicIntEnable(int intVec)
-{
-    ULONG tmp;
-    ULONG srAddr;
-
-    srAddr = SrcVecTable[intVec].srcAddr;  /* Retrieve src Vec/Prio register */
-    tmp = sysEUMBBARRead(srAddr);
-    tmp &= ~EPIC_VEC_PRI_MASK;             /* Clear the mask bit */
-    tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16);   /* Set priority to Default - CLH */
-    tmp |= intVec;				           /* Set Vector number */
-    sysEUMBBARWrite(srAddr, tmp);
-
-    return;
-    }
-
-/****************************************************************************
- *  epicIntDisable - Disable an interrupt source
- *
- *  This routine sets the mask bit of an external, an internal or
- *  a Timer register to disable the interrupt.
- *
- *  RETURNS:  OK or ERROR
- *
- */
-
-void epicIntDisable
-    (
-    int intVec        /* Interrupt vector number */
-    )
-    {
-
-    ULONG tmp, srAddr;
-
-    srAddr = SrcVecTable[intVec].srcAddr;
-    tmp = sysEUMBBARRead(srAddr);
-    tmp |= 0x80000000;                      /* Set the mask bit */
-    sysEUMBBARWrite(srAddr, tmp);
-    return;
-    }
-
-/****************************************************************************
- * epicIntSourceConfig - Set properties of an interrupt source
- *
- * This function sets interrupt properites (Polarity, Sense, Interrupt
- * Prority, and Interrupt Vector) of an Interrupt Source.  The properties
- * can be set when the current source is not in-request or in-service,
- * which is determined by the Activity bit.  This routine return ERROR
- * if the the Activity bit is 1 (in-request or in-service).
- *
- * This function assumes that the Source Vector/Priority register (input)
- * is a valid address.
- *
- * RETURNS:  OK or ERROR
- */
-
-int epicIntSourceConfig
-    (
-    int   Vect,                         /* interrupt source vector number */
-    int   Polarity,                     /* interrupt source polarity */
-    int   Sense,                        /* interrupt source Sense */
-    int   Prio                          /* interrupt source priority */
-    )
-
-    {
-    ULONG tmp, newVal;
-    ULONG actBit, srAddr;
-
-    srAddr = SrcVecTable[Vect].srcAddr;
-    tmp = sysEUMBBARRead(srAddr);
-    actBit = (tmp & 40000000) >> 30;    /* retrieve activity bit - bit 30 */
-    if (actBit == 1)
-	return ERROR;
-
-    tmp &= 0xff30ff00;     /* Erase previously set P,S,Prio,Vector bits */
-    newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect;
-    sysEUMBBARWrite(srAddr, tmp | newVal );
-    return (OK);
-    }
-
-/****************************************************************************
- * epicIntAck - acknowledge an interrupt
- *
- * This function reads the Interrupt acknowldge register and return
- * the vector number of the highest pending interrupt.
- *
- * RETURNS: Interrupt Vector number.
- */
-
-unsigned int epicIntAck(void)
-{
-    return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG ));
-}
-
-/****************************************************************************
- * epicEOI - signal an end of interrupt
- *
- * This function writes 0x0 to the EOI register to signal end of interrupt.
- * It is usually called after an interrupt routine is served.
- *
- * RETURNS: None
- */
-
-void epicEOI(void)
-    {
-    sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0);
-    }
-
-/****************************************************************************
- *  epicCurTaskPrioSet - sets the priority of the Processor Current Task
- *
- *  This function should be called after epicInit() to lower the priority
- *  of the processor current task.
- *
- *  RETURNS:  OK or ERROR
- */
-
-int epicCurTaskPrioSet
-    (
-    int prioNum                 /* New priority value */
-    )
-    {
-
-    if ( (prioNum < 0) || (prioNum > 0xF))
-	return ERROR;
-    sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum);
-    return OK;
-    }
-
-
-/************************************************************************
- * function: epicIntTaskGet
- *
- * description: Get value of processor current interrupt task priority register
- *
- * note:
- ***********************************************************************/
-unsigned char epicIntTaskGet()
-{
-  /* get the interrupt task priority register */
-    ULONG reg;
-    unsigned char rec;
-
-    reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG );
-    rec = ( reg & 0x0F );
-    return rec;
-}
-
-
-/**************************************************************
- * function: epicISR
- *
- * description: EPIC service routine called by the core exception
- *              at 0x500
- *
- * note:
- **************************************************************/
-unsigned int epicISR(void)
-{
-   return 0;
-}
-
-
-/************************************************************
- * function: epicModeGet
- *
- * description: query EPIC mode, return 0 if pass through mode
- *                               return 1 if mixed mode
- *
- * note:
- *************************************************************/
-unsigned int epicModeGet(void)
-{
-    ULONG val;
-
-    val = sysEUMBBARRead( EPIC_GLOBAL_REG );
-    return (( val & 0x20000000 ) >> 29);
-}
-
-
-/*********************************************
- * function: epicConfigGet
- *
- * description: Get the EPIC interrupt Configuration
- *              return 0 if not error, otherwise return 1
- *
- * note:
- ********************************************/
-void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable)
-{
-    ULONG val;
-
-    val = sysEUMBBARRead( EPIC_INT_CONF_REG );
-    *clkRatio = ( val & 0x70000000 ) >> 28;
-    *serEnable = ( val & 0x8000000 ) >> 27;
-}
-
-
-/*******************************************************************
- *  sysEUMBBARRead - Read a 32-bit EUMBBAR register
- *
- *  This routine reads the content of a register in the Embedded
- *  Utilities Memory Block, and swaps to big endian before returning
- *  the value.
- *
- *  RETURNS:  The content of the specified EUMBBAR register.
- */
-
-ULONG sysEUMBBARRead
-    (
-    ULONG regNum
-    )
-    {
-    ULONG temp;
-
-    temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum);
-    return ( LONGSWAP(temp));
-    }
-
-/*******************************************************************
- *  sysEUMBBARWrite - Write a 32-bit EUMBBAR register
- *
- *  This routine swaps the value to little endian then writes it to
- *  a register in the Embedded Utilities Memory Block address space.
- *
- *  RETURNS: N/A
- */
-
-void sysEUMBBARWrite
-    (
-    ULONG regNum,               /* EUMBBAR register address */
-    ULONG regVal                /* Value to be written */
-    )
-    {
-
-    *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal);
-    return ;
-    }
-
-
-/********************************************************
- * function: epicVendorId
- *
- * description: return the EPIC Vendor Identification
- *              register:
- *
- *              siliccon version, device id, and vendor id
- *
- * note:
- ********************************************************/
-void epicVendorId
-   (
-    unsigned int *step,
-    unsigned int *devId,
-    unsigned int *venId
-   )
-   {
-    ULONG val;
-    val = sysEUMBBARRead( EPIC_VENDOR_ID_REG );
-    *step  = ( val & 0x00FF0000 ) >> 16;
-    *devId = ( val & 0x0000FF00 ) >> 8;
-    *venId = ( val & 0x000000FF );
-    }
-
-/**************************************************
- * function: epicFeatures
- *
- * description: return the number of IRQ supported,
- *              number of CPU, and the version of the
- *              OpenEPIC
- *
- * note:
- *************************************************/
-void epicFeatures
-    (
-    unsigned int *noIRQs,
-    unsigned int *noCPUs,
-    unsigned int *verId
-    )
-    {
-    ULONG val;
-
-    val = sysEUMBBARRead( EPIC_FEATURES_REG );
-    *noIRQs  = ( val & 0x07FF0000 ) >> 16;
-    *noCPUs  = ( val & 0x00001F00 ) >> 8;
-    *verId   = ( val & 0x000000FF );
-}
-
-
-/*********************************************************
- * function: epciTmFrequncySet
- *
- * description: Set the timer frequency reporting register
- ********************************************************/
-void epicTmFrequencySet( unsigned int frq )
-{
-    sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq);
-}
-
-/*******************************************************
- * function: epicTmFrequncyGet
- *
- * description: Get the current value of the Timer Frequency
- * Reporting register
- *
- ******************************************************/
-unsigned int epicTmFrequencyGet(void)
-{
-    return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ;
-}
-
-
-/****************************************************
- * function: epicTmBaseSet
- *
- * description: Set the #n global timer base count register
- *              return 0 if no error, otherwise return 1.
- *
- * note:
- ****************************************************/
-unsigned int epicTmBaseSet
-    (
-    ULONG srcAddr,         /* Address of the Timer Base register */
-    unsigned int cnt,    /* Base count */
-    unsigned int inhibit   /* 1 - count inhibit */
-    )
-{
-
-    unsigned int val = 0x80000000;
-    /* First inhibit counting the timer */
-    sysEUMBBARWrite(srcAddr, val) ;
-
-    /* set the new value */
-    val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31);
-    sysEUMBBARWrite(srcAddr, val) ;
-    return 0;
-}
-
-/***********************************************************************
- * function: epicTmBaseGet
- *
- * description: Get the current value of the global timer base count register
- *              return 0 if no error, otherwise return 1.
- *
- * note:
- ***********************************************************************/
-unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val )
-{
-    *val = sysEUMBBARRead( srcAddr );
-    *val = *val & 0x7fffffff;
-    return 0;
-}
-
-/***********************************************************
- * function: epicTmCountGet
- *
- * description: Get the value of a given global timer
- *              current count register
- *              return 0 if no error, otherwise return 1
- * note:
- **********************************************************/
-unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val )
-{
-    *val = sysEUMBBARRead( srcAddr );
-    *val = *val & 0x7fffffff;
-    return 0;
-}
-
-
-/***********************************************************
- * function: epicTmInhibit
- *
- * description: Stop counting of a given global timer
- *              return 0 if no error, otherwise return 1
- *
- * note:
- ***********************************************************/
-unsigned int epicTmInhibit( unsigned int srcAddr )
-{
-    ULONG val;
-
-    val = sysEUMBBARRead( srcAddr );
-    val |= 0x80000000;
-    sysEUMBBARWrite( srcAddr, val );
-    return 0;
-}
-
-/******************************************************************
- * function: epicTmEnable
- *
- * description: Enable counting of a given global timer
- *              return 0 if no error, otherwise return 1
- *
- * note:
- *****************************************************************/
-unsigned int epicTmEnable( ULONG srcAddr )
-{
-    ULONG val;
-
-    val = sysEUMBBARRead( srcAddr );
-    val &= 0x7fffffff;
-    sysEUMBBARWrite( srcAddr, val );
-    return 0;
-}
-
-void epicSourcePrint(int Vect)
-    {
-    ULONG srcVal;
-
-    srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr);
-    PRINT("%s\n", SrcVecTable[Vect].srcName);
-    PRINT("Address   = 0x%lx\n", SrcVecTable[Vect].srcAddr);
-    PRINT("Vector    = %ld\n", (srcVal & 0x000000FF) );
-    PRINT("Mask      = %ld\n", srcVal >> 31);
-    PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30);
-    PRINT("Polarity  = %ld\n", (srcVal & 0x00800000) >> 23);
-    PRINT("Sense     = %ld\n", (srcVal & 0x00400000) >> 22);
-    PRINT("Priority  = %ld\n", (srcVal & 0x000F0000) >> 16);
-    }
diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S
deleted file mode 100644
index 52d19aa..0000000
--- a/cpu/mpc824x/drivers/epic/epic2.S
+++ /dev/null
@@ -1,196 +0,0 @@
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- **************************************/
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/processor.h>
-
-/*********************************************
- * function: CoreExtIntEnable
- *
- * description: Enable 603e core external interrupt
- *
- * note: mtmsr is context-synchronization
- **********************************************/
-		.text
-		.align 2
-	.global CoreExtIntEnable
-CoreExtIntEnable:
-	 mfmsr    r3
-
-	 ori      r3,r3,0x8000         /* enable external interrupt */
-	 mtmsr    r3
-
-	 bclr 20, 0
-
-/*******************************************
- * function: CoreExtIntDisable
- *
- * description: Disable 603e core external interrupt
- *
- * note:
- *******************************************/
-		.text
-		.align 2
-	.global CoreExtIntDisable
-CoreExtIntDisable:
-	mfmsr    r4
-
-	xor	r3,r3,r3
-	or      r3,r3,r4
-
-	andis.	r4,r4,0xffff
-	andi.   r3,r3,0x7fff         /* disable external interrupt */
-
-	or      r3,r3,r4
-	mtmsr    r3
-
-	bclr 20, 0
-
-/*********************************************************
- * function: epicEOI
- *
- * description: signal the EOI and restore machine status
- *       Input: r3 - value of eumbbar
- *       Output: r3 - value of eumbbar
- *               r4 - ISR vector value
- * note:
- ********************************************************/
-		.text
-		.align 2
-	.global epicEOI
-epicEOI:
-	lis	r5,0x0006	        /* Build End Of Interrupt Register offset */
-	ori	r5,r5,0x00b0
-	xor	r7,r7,r7	        /* Clear r7 */
-	stwbrx	r7,r5,r3	    /* Save r7, writing to this register will
-					     * intidate the end of processing the
-					     * highest interrupt.
-			     */
-	sync
-
-	/* ---RESTORE MACHINE STATE */
-	mfmsr	r13		        /* Clear Recoverable Interrupt bit in MSR */
-	or      r7,r7,r13
-
-	andis.  r7,r7,0xffff
-	andi.	r13,r13,0x7ffd	/* (and disable interrupts) */
-	or      r13,r13,r7
-	mtmsr	r13
-
-	lwz   r13,0x1c(r1)      /* pull ctr */
-	mtctr r13
-
-	lwz   r13,0x18(r1)      /* pull xer */
-	mtctr r13
-
-	lwz   r13,0x14(r1)      /* pull lr */
-	mtctr r13
-
-	lwz	    r13,0x10(r1)	/* Pull SRR1 from stack */
-	mtspr   SRR1,r13	    /* Restore SRR1 */
-
-	lwz	    r13,0xc(r1)	    /* Pull SRR0 from stack */
-	mtspr   SRR0,r13	    /* Restore SRR0 */
-
-	lwz	    r13,0x8(r1)	    /* Pull User stack pointer from stack */
-	mtspr   SPRG1,r13	    /* Restore SPRG1 */
-
-	lwz	r4,0x4(r1)          /* vector value */
-	lwz	r3,0x0(r1)          /* eumbbar */
-	sync
-
-	addi	r1,r1,0x20	/* Deallocate stack */
-	mtspr   SPRG0,r1	/* Save updated Supervisor stack pointer */
-	mfspr   r1,SPRG1	/* Restore User stack pointer */
-
-	bclr     20,0
-
-/***********************************************************
- * function: exception routine called by exception vector
- *           at 0x500, external interrupt
- *
- * description: Kahlua EPIC controller
- *
- * input:  r3 - content of eumbbar
- * output: r3 - ISR return value
- *         r4 - Interrupt vector number
- * note:
- ***********************************************************/
-
-       .text
-	   .align 2
-       .global epic_exception
-
-epic_exception:
-
-	/*---SAVE MACHINE STATE TO A STACK */
-	mtspr   SPRG1,r1	/* Save User stack pointer to SPRG1 */
-	mfspr	r1,SPRG0	/* Load Supervisor stack pointer into r1 */
-
-	stwu	r3,-0x20(r1)	/* Push the value of eumbbar onto stack */
-
-	mfspr	r3,SPRG1	/* Push User stack pointer onto stack */
-	stw	    r3,0x8(r1)
-	mfspr	r3,SRR0	    /* Push SRR0 onto stack */
-	stw	    r1,0xc(r1)
-	mfspr	r3,SRR1	    /* Push SRR1 onto stack */
-	stw	    r3,0x10(r1)
-	mflr    r3
-	stw     r3,0x14(r1) /* Push LR */
-	mfxer   r3
-	stw     r3,0x18(r1) /* Push Xer */
-	mfctr   r3
-	stw     r3,0x1c(r1) /* Push CTR */
-
-	mtspr	SPRG0,r1	/* Save updated Supervisor stack pointer
-					 * value to SPRG0
-			 */
-	mfmsr	r3
-	ori	    r3,r3,0x0002	/* Set Recoverable Interrupt bit in MSR */
-	mtmsr	r3
-
-	/* ---READ IN THE EUMBAR REGISTER */
-    lwz     r6,0(r1)       /* this is eumbbar */
-    sync
-
-	/* ---READ EPIC REGISTER:	PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */
-	lis	r5,0x0006	        /* Build Interrupt Acknowledge Register
-					     * offset
-			     */
-	ori	r5,r5,0x00a0
-	lwbrx	r7,r5,r6    /* Load interrupt vector into r7 */
-	sync
-
-	/* --MASK OFF ALL BITS EXCEPT THE VECTOR */
-	xor	r3,r3,r3
-    xor r4,r4,r4
-	or    r3, r3, r6        /*  eumbbar in r3 */
-	andi. r4,r7,0x00ff	/* Mask off bits, vector in r4 */
-
-    stw     r4,0x04(r1)     /* save the vector value */
-
-    lis     r5,epicISR@ha
-	ori     r5,r5,epicISR@l
-	mtlr    r5
-	blrl
-
-    xor   r30,r30,r30
-	or    r30,r30,r3        /* save the r3 which containts the return value from epicISR */
-
-	/* ---READ IN THE EUMBAR REGISTER */
-    lwz     r3,0(r1)
-    sync
-
-    lis     r5,epicEOI@ha
-	ori     r5,r5,epicEOI@l
-	mtlr    r5
-	blrl
-
-    xor  r3,r3,r3
-	or   r3,r3,r30           /* restore the ISR return value  */
-
-	bclr     20,0
diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/cpu/mpc824x/drivers/epic/epicutil.S
deleted file mode 100644
index 4877050..0000000
--- a/cpu/mpc824x/drivers/epic/epicutil.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- *
- * This file contains two commonly used
- * lower level utility routines.
- *
- * The utility routines are also in other
- * Kahlua device driver libraries. The
- * need to be linked in only once.
- **************************************/
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-/**********************************************************
- * function: load_runtime_reg
- *
- * input:  r3 - value of eumbbar
- *         r4 - register offset in embedded utility space
- *
- * output: r3 - register content
- **********************************************************/
-      .text
-      .align 2
-      .global load_runtime_reg
-
-load_runtime_reg:
-
-		  xor r5,r5,r5
-	  or  r5,r5,r3       /* save eumbbar */
-
-	      lwbrx	r3,r4,r5
-	      sync
-
-	      bclr 20, 0
-
-/****************************************************************
- * function: store_runtime_reg
- *
- * input: r3 - value of eumbbar
- *        r4 - register offset in embedded utility space
- *        r5 - new value to be stored
- *
- ****************************************************************/
-	   .text
-	   .align 2
-	   .global store_runtime_reg
-store_runtime_reg:
-
-		  xor r0,r0,r0
-
-	      stwbrx r5,  r4, r3
-	      sync
-
-		  bclr   20,0