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authorwdenk <wdenk>2002-12-07 00:20:59 +0000
committerwdenk <wdenk>2002-12-07 00:20:59 +0000
commit7c7a23bd5a0bc149d2edd665ec46381726b24e0c (patch)
treed859f82ea2561180db2ffd7569f0b9007d710769 /cpu/mpc824x/drivers/epic
parent1f53a41603b9093c59741f4208fef0ab3790d6ce (diff)
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* Patch by Hans-Joerg Frieden, 06 Dec 2002
Fix misc problems with AmigaOne support * Patch by Chris Hallinan, 3 Dec 2002: minor cleanup to the MPC8245 EPIC driver * Patch by Pierre Aubert , 28 Nov 2002 Add support for external (SIU) interrupts on MPC8xx * Patch by Pierre Aubert , 28 Nov 2002 Fix nested syscalls bug in standalone applications * Patch by David Müller, 27 Nov 2002: fix output of "pciinfo" command for CardBus bridge devices. * Fix bug in TQM8260 board detection - boards got stuck when board ID was not readable
Diffstat (limited to 'cpu/mpc824x/drivers/epic')
-rw-r--r--cpu/mpc824x/drivers/epic/epic.h3
-rw-r--r--cpu/mpc824x/drivers/epic/epic1.c19
2 files changed, 15 insertions, 7 deletions
diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h
index 7751db2..17e4afb 100644
--- a/cpu/mpc824x/drivers/epic/epic.h
+++ b/cpu/mpc824x/drivers/epic/epic.h
@@ -108,6 +108,9 @@
#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
+#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */
+#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */
+
/* Error code */
#define OK 0
diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c
index 362e129..eb7ed40 100644
--- a/cpu/mpc824x/drivers/epic/epic1.c
+++ b/cpu/mpc824x/drivers/epic/epic1.c
@@ -70,6 +70,10 @@ void epicInit
tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
tmp |= 0xa0000000; /* Set the Global Conf. register */
sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
+ /*
+ * Wait for EPIC to reset - CLH
+ */
+ while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */
@@ -81,7 +85,8 @@ void epicInit
sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
}
- while (epicIntAck() != 0xff); /* Clear all pending interrupts */
+ while (epicIntAck() != 0xff) /* Clear all pending interrupts */
+ epicEOI();
}
/****************************************************************************
@@ -92,18 +97,18 @@ void epicInit
*
* RETURNS: None
*/
-void epicIntEnable
- (
- int intVec /* Interrupt Vector Number */
- )
- {
+void epicIntEnable(int intVec)
+{
ULONG tmp;
ULONG srAddr;
srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */
tmp = sysEUMBBARRead(srAddr);
- tmp &= 0x7fffffff; /* Clear the mask bit */
+ tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */
+ tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */
+ tmp |= intVec; /* Set Vector number */
sysEUMBBARWrite(srAddr, tmp);
+
return;
}