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| author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 15:23:46 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-12-12 19:51:59 +0800 |
| commit | 956ae96db2cdcc6e17f0b28aa97484717957b4c8 (patch) | |
| tree | c9253a5325e8db63b4e7abdb5635d8415078f4df /cpu/mpc8220/dramSetup.h | |
| parent | 658971fe22d1beb640ede108419d75b2919a2d80 (diff) | |
| download | u-boot-imx-956ae96db2cdcc6e17f0b28aa97484717957b4c8.zip u-boot-imx-956ae96db2cdcc6e17f0b28aa97484717957b4c8.tar.gz u-boot-imx-956ae96db2cdcc6e17f0b28aa97484717957b4c8.tar.bz2 | |
ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'cpu/mpc8220/dramSetup.h')
0 files changed, 0 insertions, 0 deletions