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authorwdenk <wdenk>2003-09-14 19:08:39 +0000
committerwdenk <wdenk>2003-09-14 19:08:39 +0000
commit35656de72996bb737d60ae0813f0b8dd4ad366c6 (patch)
tree302181223450b0dd525f27165454ed7e899894e8 /cpu/mpc5xxx/pci_mpc5200.c
parent200f8c7a4c450f3374c87b5f3a2d29d35c895758 (diff)
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* Patch by Gleb Natapov, 14 Sep 2003:
enable watchdog support for all MPC824x boards that have a watchdog * On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the "Non-octet Aligned Frame" errors we see at 100 Mbps * Patch by Sharad Gupta, 14 Sep 2003: fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
Diffstat (limited to 'cpu/mpc5xxx/pci_mpc5200.c')
-rw-r--r--cpu/mpc5xxx/pci_mpc5200.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index a890a6d..a54c5f4 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -48,9 +48,11 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
{
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
+ udelay(10);
*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+ udelay(10);
return 0;
}
@@ -59,9 +61,11 @@ static int mpc5200_write_config_dword(struct pci_controller *hose,
{
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
+ udelay(10);
out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+ udelay(10);
return 0;
}