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| author | Anatolij Gustschin <agust@denx.de> | 2008-11-13 18:08:57 +0100 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-12-03 22:47:01 -0600 |
| commit | dd332e18d082de75eca3fc2c7c778f5d4571a096 (patch) | |
| tree | 94b5fe6ea33556610852de749ffb9ccb8450511c /cpu/mpc5xx/traps.c | |
| parent | a2cd50ed6ef0ac6b127b3d6db756979a8336718d (diff) | |
| download | u-boot-imx-dd332e18d082de75eca3fc2c7c778f5d4571a096.zip u-boot-imx-dd332e18d082de75eca3fc2c7c778f5d4571a096.tar.gz u-boot-imx-dd332e18d082de75eca3fc2c7c778f5d4571a096.tar.bz2 | |
85xx: socrates: fix DDR SDRAM tlb entry configuration
since commit be0bd8234b9777ecd63c4c686f72af070d886517
tlb entry for socrates DDR SDRAM will be reconfigured
by setup_ddr_tlbs() from initdram() causing an
inconsistency with previously configured DDR SDRAM tlb
entry from tlb_table:
socrates>l2cam 7 9
IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS
7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX
8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX
9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX
This patch makes the presence of the DDR SDRAM tlb entry in
the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
inconsistency.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/mpc5xx/traps.c')
0 files changed, 0 insertions, 0 deletions