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| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-06-07 20:51:56 +0900 |
|---|---|---|
| committer | Shinya Kuribayashi <shinya.kuribayashi@necel.com> | 2008-06-07 20:51:56 +0900 |
| commit | 8bde63eb3f79d68f693201528dafc8ae7aa087de (patch) | |
| tree | 2078062f2ecb762e6b15b5b3e628a946ca409520 /cpu/mips | |
| parent | 7daf2ebe9196dd67131a06d85049c3a8a08ca413 (diff) | |
| download | u-boot-imx-8bde63eb3f79d68f693201528dafc8ae7aa087de.zip u-boot-imx-8bde63eb3f79d68f693201528dafc8ae7aa087de.tar.gz u-boot-imx-8bde63eb3f79d68f693201528dafc8ae7aa087de.tar.bz2 | |
[MIPS] Rename Alchemy processor configs into CONFIG_SOC_*
CONFIG_SOC_AU1X00
Common Alchemy Au1x00 stuff. All Alchemy processor based machines
need to have this config as a system type specifier.
CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550
Machine type specifiers. Each port should have one of aboves.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mips')
| -rw-r--r-- | cpu/mips/au1x00_eth.c | 12 | ||||
| -rw-r--r-- | cpu/mips/au1x00_serial.c | 4 | ||||
| -rw-r--r-- | cpu/mips/au1x00_usb_ohci.c | 2 |
3 files changed, 9 insertions, 9 deletions
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index d70c5fe..aeb9662 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,7 +23,7 @@ */ #include <config.h> -#ifdef CONFIG_AU1X00 +#ifdef CONFIG_SOC_AU1X00 #if defined(CFG_DISCOVER_PHY) #error "PHY not supported yet" @@ -33,20 +33,20 @@ /* I assume ethernet behaves like au1000 */ -#ifdef CONFIG_AU1000 +#ifdef CONFIG_SOC_AU1000 /* Base address differ between cpu:s */ #define ETH0_BASE AU1000_ETH0_BASE #define MAC0_ENABLE AU1000_MAC0_ENABLE #else -#ifdef CONFIG_AU1100 +#ifdef CONFIG_SOC_AU1100 #define ETH0_BASE AU1100_ETH0_BASE #define MAC0_ENABLE AU1100_MAC0_ENABLE #else -#ifdef CONFIG_AU1500 +#ifdef CONFIG_SOC_AU1500 #define ETH0_BASE AU1500_ETH0_BASE #define MAC0_ENABLE AU1500_MAC0_ENABLE #else -#ifdef CONFIG_AU1550 +#ifdef CONFIG_SOC_AU1550 #define ETH0_BASE AU1550_ETH0_BASE #define MAC0_ENABLE AU1550_MAC0_ENABLE #else @@ -308,4 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } -#endif /* CONFIG_AU1X00 */ +#endif /* CONFIG_SOC_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 42c668e..ec10ac0 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -27,7 +27,7 @@ #include <config.h> -#ifdef CONFIG_AU1X00 +#ifdef CONFIG_SOC_AU1X00 #include <common.h> #include <asm/au1x00.h> @@ -132,4 +132,4 @@ int serial_tstc (void) } return 0; } -#endif /* CONFIG_SERIAL_AU1X00 */ +#endif /* CONFIG_SOC_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index dbf72dc..e03b125 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -35,7 +35,7 @@ #include <config.h> -#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) +#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI) /* #include <pci.h> no PCI on the AU1x00 */ |