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| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 21:30:07 +0900 |
|---|---|---|
| committer | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 21:30:07 +0900 |
| commit | d43d43ef2845af309c25a64bb9c2c5fb3261bc23 (patch) | |
| tree | 8110ca5dee67d093aebfee728e838e3fdd89f7d5 /cpu/mips | |
| parent | 26138623230ca2bad3c78e05a65527ea70c8b688 (diff) | |
| download | u-boot-imx-d43d43ef2845af309c25a64bb9c2c5fb3261bc23.zip u-boot-imx-d43d43ef2845af309c25a64bb9c2c5fb3261bc23.tar.gz u-boot-imx-d43d43ef2845af309c25a64bb9c2c5fb3261bc23.tar.bz2 | |
[MIPS] Initialize CP0 Cause before setting up CP0 Status register
Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mips')
| -rw-r--r-- | cpu/mips/start.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/mips/start.S b/cpu/mips/start.S index fde2944..0ecdd83 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -211,6 +211,9 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI + /* WP(Watch Pending), SW0/1 should be cleared. */ + mtc0 zero, CP0_CAUSE + /* STATUS register */ #ifdef CONFIG_TB0229 li k0, ST0_CU0 @@ -221,9 +224,6 @@ reset: and k0, k1 mtc0 k0, CP0_STATUS - /* CAUSE register */ - mtc0 zero, CP0_CAUSE - /* Init Timer */ mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE |