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| author | Stefan Roese <sr@denx.de> | 2007-03-07 16:39:36 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-07 16:39:36 +0100 |
| commit | e2ebe696818939e2b974628be9c921ea3fe9de13 (patch) | |
| tree | c7c7572314c55bd142774f3bf45ab7fdd01ee02e /cpu/mips/incaip_clock.c | |
| parent | fdd1d6dcc97c595bd9d598ed3b22a7038781272c (diff) | |
| download | u-boot-imx-e2ebe696818939e2b974628be9c921ea3fe9de13.zip u-boot-imx-e2ebe696818939e2b974628be9c921ea3fe9de13.tar.gz u-boot-imx-e2ebe696818939e2b974628be9c921ea3fe9de13.tar.bz2 | |
[PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM's
This patch fixes a problem that occurs when 2 DIMM's are
used. This problem was first spotted and fixed by Gerald Jackson
<gerald.jackson@reaonixsecurity.com> but this patch fixes the
problem in a little more clever way.
This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.
As this feature is new to the "old" 44x SPD DDR driver, it
has to be enabled via the CONFIG_PROG_SDRAM_TLB define.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/mips/incaip_clock.c')
0 files changed, 0 insertions, 0 deletions