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| author | Shinya Kuribayashi <shinya.kuribayashi@necel.com> | 2008-04-08 16:20:35 +0900 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-04-17 14:54:23 -0700 |
| commit | 188e94c370621708d13547d58dbc6ed3c5602aa8 (patch) | |
| tree | bfc01a68445ca78cd5c03d12dd5ec0b83ebdd2cc /cpu/mips/cpu.c | |
| parent | 8f2a68a07c058fca1d413e54f71c2e7e78a74ed4 (diff) | |
| download | u-boot-imx-188e94c370621708d13547d58dbc6ed3c5602aa8.zip u-boot-imx-188e94c370621708d13547d58dbc6ed3c5602aa8.tar.gz u-boot-imx-188e94c370621708d13547d58dbc6ed3c5602aa8.tar.bz2 | |
cpu/mips/cpu.c: Fix flush_cache bug
Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Diffstat (limited to 'cpu/mips/cpu.c')
| -rw-r--r-- | cpu/mips/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 8b43d8e..e267bba 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size) unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Writeback_Inv_D, start_addr); - cache_op(Hit_Invalidate_I, start_addr); + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); if (addr == aend) break; addr += lsize; |