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| author | Stefan Roese <sr@denx.de> | 2009-01-21 17:20:20 +0100 |
|---|---|---|
| committer | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2009-01-27 23:06:58 +0900 |
| commit | 03d3bfb00806b5441f1871c7408c1749863e0fdc (patch) | |
| tree | 6d77e7ec95dbaa15b0d1aa1aaf89f5f0c39f3932 /cpu/mips/cpu.c | |
| parent | 8f86a3636ef88427f880610638e80991adc41896 (diff) | |
| download | u-boot-imx-03d3bfb00806b5441f1871c7408c1749863e0fdc.zip u-boot-imx-03d3bfb00806b5441f1871c7408c1749863e0fdc.tar.gz u-boot-imx-03d3bfb00806b5441f1871c7408c1749863e0fdc.tar.bz2 | |
MIPS: Add flush_dcache_range() and invalidate_dcache_range()
This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mips/cpu.c')
| -rw-r--r-- | cpu/mips/cpu.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index b7180b0..d5a1604 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -65,6 +65,34 @@ void flush_cache(ulong start_addr, ulong size) } } +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { write_c0_entrylo0(low0); |