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| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 21:30:07 +0900 |
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| committer | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 21:30:07 +0900 |
| commit | decaba6f5cf386d569ac3997bebb871b966c6b18 (patch) | |
| tree | 71f09ba3ea48d9ae4a00d7e6735f71980e7fa2f5 /cpu/mips/cache.S | |
| parent | d43d43ef2845af309c25a64bb9c2c5fb3261bc23 (diff) | |
| download | u-boot-imx-decaba6f5cf386d569ac3997bebb871b966c6b18.zip u-boot-imx-decaba6f5cf386d569ac3997bebb871b966c6b18.tar.gz u-boot-imx-decaba6f5cf386d569ac3997bebb871b966c6b18.tar.bz2 | |
[MIPS] Cleanup CP0 Status initialization
Add setup_c0_status from Linux. For the moment we disable interrupts, set
CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for
reset-time configuration and will work well across most processors.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mips/cache.S')
0 files changed, 0 insertions, 0 deletions