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authorWolfgang Denk <wd@denx.de>2008-06-11 22:48:09 +0200
committerWolfgang Denk <wd@denx.de>2008-06-11 22:48:09 +0200
commit1a5017601f6d17caedaa2bf069485d3e4155f1c0 (patch)
tree342b39d2a55eb4ebaf8b772bc8b74db4318d5eb7 /cpu/mips/cache.S
parentcdeb62e20d94005f2e80604fda03b498c3a6f704 (diff)
parent79b51ff8205f0354d5300570614c1d2db499679c (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-mips
Diffstat (limited to 'cpu/mips/cache.S')
-rw-r--r--cpu/mips/cache.S7
1 files changed, 3 insertions, 4 deletions
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 1b0efc3..ee5d411 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -23,7 +23,6 @@
*/
#include <config.h>
-#include <version.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
@@ -41,7 +40,7 @@
*/
#define MIPS_MAX_CACHE_SIZE 0x10000
-#define INDEX_BASE KSEG0
+#define INDEX_BASE CKSEG0
.macro cache_op op addr
.set push
@@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
/*
* Now clear that much memory starting from zero.
*/
- PTR_LI a0, KSEG1
+ PTR_LI a0, CKSEG1
PTR_ADDU a1, a0, v0
2: PTR_ADDIU a0, 64
f_fill64 a0, -64, zero
@@ -319,7 +318,7 @@ LEAF(dcache_enable)
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
- li a1, K0BASE - CACHE_LOCK_SIZE
+ li a1, CKSEG0 - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CFG_CACHELINE_SIZE