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authorwdenk <wdenk>2003-10-09 20:09:04 +0000
committerwdenk <wdenk>2003-10-09 20:09:04 +0000
commit5da627a424b3ad2d38a81886ba4a18e5123a6788 (patch)
tree13d274effe8b9c740a07f4cb47989f3215c20bb4 /cpu/mips/cache.S
parent15647dc7fd86bbaeb68740929ecb9f8473c7ceae (diff)
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* Patch by Steven Scholz, 10 Oct 2003
- Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003: - Endian swap ATA identity for all big endian CPUs, not just PPC - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize args to linux - add support for dbau1x00 board (MIPS32)
Diffstat (limited to 'cpu/mips/cache.S')
-rw-r--r--cpu/mips/cache.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 01fbb2f..aad76e0 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -250,10 +250,10 @@ dcache_disable:
* RETURNS: N/A
*
*/
-#if defined(CONFIG_INCA_IP)
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
-#elif defined(CONFIG_PURPLE)
+#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+#else
+# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock