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authorwdenk <wdenk>2004-01-02 15:01:32 +0000
committerwdenk <wdenk>2004-01-02 15:01:32 +0000
commit63f3491242df8e6bd1b5df7296f28959989e2eaf (patch)
tree7af4bc5c75cdc9ee45cc4c7c6e144a79845b6ae6 /cpu/mips/au1x00_eth.c
parentd4ca31c40e8888b36635967522ec7ea03fd7e70b (diff)
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* Patch by André Schwarz, 8 Dec 2003:
fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): - TX and RX deskriptors must be quad-word aligned - does not work with only one TX deskriptor - standard reset method does not work * Patch by Masami Komiya, 08 Dec 2003: add RTL8139 ethernet driver * Patches by Ed Okerson, 07 Dec 2003: - fix ethernet for the AU1x00 processors in little-endian mode. - extend memsetup.S for the AU1x00 processors in BE and LE modes
Diffstat (limited to 'cpu/mips/au1x00_eth.c')
-rw-r--r--cpu/mips/au1x00_eth.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index ae51b75..4f68a9b 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -187,19 +187,24 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
}
/* Put mac addr in little endian */
- /* FIXME Check this for little endian mode */
#define ea eth_get_dev()->enetaddr
*mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
(ea[1] << 8) | (ea[0] ) ;
#undef ea
-
*mac_mcast_low = 0;
*mac_mcast_high = 0;
+ /* Make sure the MAC buffer is in the correct endian mode */
+#ifdef __LITTLE_ENDIAN
+ *mac_ctrl = MAC_FULL_DUPLEX;
+ udelay(1);
+ *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#else
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#endif
return(1);
}