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authorWolfgang Denk <wd@pollux.(none)>2005-09-25 00:53:22 +0200
committerWolfgang Denk <wd@pollux.(none)>2005-09-25 00:53:22 +0200
commit265817c7e6e55f1c2d05b8aa2080145291968b2e (patch)
tree039a6759c8fcfe262f0af106e7c5ac746d19478e /cpu/mips/au1x00_eth.c
parentb63de2c053999d95c71a93745c410a2ffc65327f (diff)
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Add support for AMD's Pb1x00 eval board;
add MII routines to the au1x00 ethernet driver; add USB ohci driver (work in progress) Patch by Thomas Sailer, 20 Jan 2005
Diffstat (limited to 'cpu/mips/au1x00_eth.c')
-rw-r--r--cpu/mips/au1x00_eth.c69
1 files changed, 63 insertions, 6 deletions
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index 35c07b1..b7a7652 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -13,7 +13,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -25,8 +25,8 @@
#ifdef CONFIG_AU1X00
-#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
-#error "PHY and MII not supported yet"
+#if defined(CFG_DISCOVER_PHY)
+#error "PHY not supported yet"
/* We just assume that we are running 100FD for now */
/* We all use switches, right? ;-) */
#endif
@@ -193,9 +193,9 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
/* Put mac addr in little endian */
#define ea eth_get_dev()->enetaddr
- *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
- *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
- (ea[1] << 8) | (ea[0] ) ;
+ *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
+ *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
+ (ea[1] << 8) | (ea[0] ) ;
#undef ea
*mac_mcast_low = 0;
*mac_mcast_high = 0;
@@ -236,4 +236,61 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+ *mii_control_reg = mii_control;
+
+ timedout = 20;
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+ *value = *mii_data_reg;
+ return 0;
+}
+
+int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_write busy timeout!!\n");
+ return;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+ *mii_data_reg = value;
+ *mii_control_reg = mii_control;
+ return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
+
#endif /* CONFIG_AU1X00 */