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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-10-03 12:36:39 -0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:04 +0200 |
| commit | dbbbb3abeff325855cae76e33d69d5665631443f (patch) | |
| tree | 2df59a7ac7364e4c501e228c74db3cd5f14ad3b1 /cpu/mips/asc_serial.h | |
| parent | 1c9aa76bf9013069e24258f46f4687c9f98a02d6 (diff) | |
| download | u-boot-imx-dbbbb3abeff325855cae76e33d69d5665631443f.zip u-boot-imx-dbbbb3abeff325855cae76e33d69d5665631443f.tar.gz u-boot-imx-dbbbb3abeff325855cae76e33d69d5665631443f.tar.bz2 | |
Make DDR interleaving mode work correctly
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'cpu/mips/asc_serial.h')
0 files changed, 0 insertions, 0 deletions