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authorMichal Simek <root@monstr.eu>2007-03-26 01:39:07 +0200
committerMichal Simek <root@monstr.eu>2007-03-26 01:39:07 +0200
commit1798049522f594013aea29457d46794298c6ae15 (patch)
tree966edd78aadda268b6412e616c051602f99a6094 /cpu/microblaze
parentcfc67116a706fd18b8f6a9c11a16753c5626d689 (diff)
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Support for XUPV2P board
Reset support BSP autoconfig support
Diffstat (limited to 'cpu/microblaze')
-rw-r--r--cpu/microblaze/interrupts.c6
-rw-r--r--cpu/microblaze/start.S31
2 files changed, 33 insertions, 4 deletions
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 37ed16d..2db847c 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -95,7 +95,7 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
{
struct irq_action *act;
/* irq out of range */
- if ((irq < 0) || (irq > CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS)) {
+ if ((irq < 0) || (irq > CFG_INTC_0_NUM)) {
puts ("IRQ out of range\n");
return;
}
@@ -131,7 +131,7 @@ int interrupts_init (void)
{
int i;
/* initialize irq list */
- for (i = 0; i < CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS; i++) {
+ for (i = 0; i < CFG_INTC_0_NUM; i++) {
vecs[i].handler = (interrupt_handler_t *) def_hdlr;
vecs[i].arg = (void *)i;
vecs[i].count = 0;
@@ -189,7 +189,7 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"Nr Routine Arg Count\n"
"-----------------------------\n");
- for (i = 0; i < CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS; i++) {
+ for (i = 0; i < CFG_INTC_0_NUM; i++) {
if (act->handler != (interrupt_handler_t*) def_hdlr) {
printf ("%02d %08lx %08lx %d\n", i,
(int)act->handler, (int)act->arg, act->count);
diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index bce3297..29481af 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -31,6 +31,7 @@
_start:
mts rmsr, r0 /* disable cache */
addi r1, r0, CFG_INIT_SP_OFFSET
+ addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb000 /* hex b000 opcode imm */
bslli r6, r6, 16 /* shift */
@@ -53,6 +54,23 @@ _start:
lhu r7, r1, r0
shi r7, r0, 0x2
shi r6, r0, 0x6
+/*
+ * Copy U-Boot code to TEXT_BASE
+ * solve problem with sbrk_base
+ */
+#if (CFG_RESET_ADDRESS != TEXT_BASE)
+ addi r4, r0, __end
+ addi r5, r0, __text_start
+ rsub r4, r5, r4 /* size = __end - __text_start */
+ addi r6, r0, CFG_RESET_ADDRESS /* source address */
+ addi r7, r0, 0 /* counter */
+4:
+ lw r8, r6, r7
+ sw r8, r5, r7
+ addi r7, r7, 0x4
+ cmp r8, r4, r7
+ blti r8, 4b
+#endif
#endif
#ifdef CFG_USR_EXCEP
@@ -85,6 +103,17 @@ _start:
ori r12, r12, 0xa0
mts rmsr, r12
- /* jumping to board_init */
+clear_bss:
+ /* clear BSS segments */
+ addi r5, r0, __bss_start
+ addi r4, r0, __bss_end
+ cmp r6, r5, r4
+ beqi r6, 3f
+2:
+ swi r0, r5, 0 /* write zero to loc */
+ addi r5, r5, 4 /* increment to next loc */
+ cmp r6, r5, r4 /* check if we have reach the end */
+ bnei r6, 2b
+3: /* jumping to board_init */
brai board_init
1: bri 1b